wrcore_v2: upgrated wrc_periph module

9b1a65ab · Grzegorz Daniluk · 71f2a5e3 · 9b1a65ab
Commit 9b1a65ab authored Nov 29, 2011 by Grzegorz Daniluk
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Showing with 61 additions and 49 deletions

wrc_periph.vhd modules/wrc_core/wrc_periph.vhd +61 -49

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--- a/modules/wrc_core/wrc_periph.vhd
+++ b/modules/wrc_core/wrc_periph.vhd
@@ -32,15 +32,13 @@ use work.sysc_wbgen2_pkg.all;
 entity wrc_periph is
  generic(
-    g_phys_uart     : boolean := true;
+    g_phys_uart    : boolean := true;
-    g_virtual_uart  : boolean := false;
+    g_virtual_uart : boolean := false
-    g_owr_num_ports : natural := 1
  );
  port(
    clk_sys_i : in std_logic;
    rst_n_i   : in std_logic;
-    rst_ext_n_i : in  std_logic;
    rst_net_n_o : out std_logic;
    rst_wrc_n_o : out std_logic;
@@ -61,9 +59,8 @@ entity wrc_periph is
    uart_txd_o : out std_logic;
    -- 1-Wire
-    owr_pwren_o : out std_logic_vector(g_owr_num_ports-1 downto 0);
+    owr_en_o : out std_logic;
-    owr_en_o    : out std_logic_vector(g_owr_num_ports-1 downto 0);
+    owr_i    : in  std_logic
-    owr_i       : in  std_logic_vector(g_owr_num_ports-1 downto 0)
  );
 end wrc_periph;
@@ -72,24 +69,26 @@ architecture struct of wrc_periph is
  signal sysc_regs_i : t_sysc_in_registers;
  signal sysc_regs_o : t_sysc_out_registers;
+  signal owr_en_slv : std_logic_vector(0 downto 0);
+  signal owr_in_slv : std_logic_vector(0 downto 0);
 begin
  -- reset wrc
  process(clk_sys_i)
  begin
    if rising_edge(clk_sys_i) then
-      if(rst_ext_n_i = '0') then
+      if(rst_n_i = '0') then
-        rst_wrc_n_o <= '0';
-        rst_net_n_o <= '0';
-      elsif(sysc_regs_o.rstr_hrst_wr_o = '1' and sysc_regs_o.rstr_hrst_o = x"deadbeef") then
        rst_wrc_n_o <= '0';
        rst_net_n_o <= '0';
-      elsif(sysc_regs_o.gpsr_net_rst_o = '1') then
-        rst_wrc_n_o <= '1';
-        rst_net_n_o <= '0';
      else
-        rst_wrc_n_o <= '1';
-        rst_net_n_o <= '1';
+        if(sysc_regs_o.rstr_trig_wr_o = '1' and sysc_regs_o.rstr_trig_o = x"deadbee") then
+          rst_wrc_n_o <= not sysc_regs_o.rstr_rst_o;
+        end if;
+        rst_net_n_o <= not sysc_regs_o.gpsr_net_rst_o;
      end if;
    end if;
  end process;
@@ -116,47 +115,58 @@ begin
  sysc_regs_i.gpsr_btn1_i <= btn1_i;
  sysc_regs_i.gpsr_btn2_i <= btn2_i;
-  -- SCL/SDA
-  scl_o <= '1' when (sysc_regs_o.gpsr_fmc_scl_o = '1' and sysc_regs_o.gpsr_fmc_scl_load_o = '1') else
-           '0' when (sysc_regs_o.gpcr_fmc_scl_o = '0');
+  p_drive_i2c : process(clk_sys_i)
-  sda_o <= '1' when (sysc_regs_o.gpsr_fmc_sda_o = '1' and sysc_regs_o.gpsr_fmc_sda_load_o = '1') else
+  begin
-           '0' when (sysc_regs_o.gpcr_fmc_sda_o = '0');
+    if rising_edge(clk_sys_i) then
-  sysc_regs_i.gpsr_fmc_scl_i <= scl_i;
+      if rst_n_i = '0' then
+        scl_o <= '1';
+        sda_o <= '1';
+      else
+        if(sysc_regs_o.gpsr_fmc_sda_load_o = '1' and sysc_regs_o.gpsr_fmc_sda_o = '1') then
+          sda_o <= '1';
+        elsif(sysc_regs_o.gpcr_fmc_sda_o = '1') then
+          sda_o <= '0';
+        end if;
+        if(sysc_regs_o.gpsr_fmc_scl_load_o = '1' and sysc_regs_o.gpsr_fmc_scl_o = '1') then
+          scl_o <= '1';
+        elsif(sysc_regs_o.gpcr_fmc_scl_o = '1') then
+          scl_o <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
  sysc_regs_i.gpsr_fmc_sda_i <= sda_i;
+  sysc_regs_i.gpsr_fmc_scl_i <= scl_i;
  -- Memsize
  sysc_regs_i.hwfr_memsize_i <= memsize_i;
- --TRIG3(11 downto 0)  <= wb_addr_i(11 downto 0);
- -- TRIG3(21 downto 12) <= (others => '0');
- -- TRIG3(31 downto 28) <= wb_sel_i;
- -- TRIG3(22)           <= wb_cyc_i;
- -- TRIG3(23)           <= wb_stb_i;
- -- TRIG3(24)           <= wb_we_i;
- -- TRIG3(25)           <= wb_ack_int;
- -- TRIG0               <= wb_data_i;
- -- TRIG2(3 downto 0) <= wb_cycs_i;
- -- TRIG2(7 downto 4) <= wb_acks_o;
  ----------------------------------------
  -- SYSCON
  ----------------------------------------
-  SYSCON : wrc_syscon_wb
+  SYSCON: xwr_syscon_wb
+    generic map(
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE
+    )
    port map(
      rst_n_i   => rst_n_i,
-      wb_clk_i  => clk_sys_i,
+      clk_sys_i => clk_sys_i,
-      wb_addr_i => slave_i(0).adr(4 downto 2),  -- because address has byte granularity
-      wb_data_i => slave_i(0).dat,
+      slave_i   => slave_i(0),
-      wb_data_o => slave_o(0).dat,
+      slave_o   => slave_o(0),
-      wb_cyc_i  => '0',                 --slave_i(0).cyc,
-      wb_sel_i  => (others => '0'),     --slave_i(0).sel,
-      wb_stb_i  => '0',                 --slave_i(0).stb,
-      wb_we_i   => '0',                 --slave_i(0).we,
-      wb_ack_o  => slave_o(0).ack,
      regs_i    => sysc_regs_i,
      regs_o    => sysc_regs_o
    );
+  --slave_o(0).ack <= '0';
+  --slave_o(0).stall <= '0';
  --------------------------------------
  -- UART
  --------------------------------------
@@ -164,7 +174,7 @@ begin
    generic map(
      g_with_virtual_uart   => g_virtual_uart,
      g_with_physical_uart  => g_phys_uart,
-      g_interface_mode      => CLASSIC,
+      g_interface_mode      => PIPELINED,
      g_address_granularity => BYTE
    )
    port map(
@@ -185,9 +195,9 @@ begin
  --------------------------------------
  ONEWIRE : xwb_onewire_master
    generic map(
-      g_interface_mode      => CLASSIC,
+      g_interface_mode      => PIPELINED,
      g_address_granularity => BYTE,
-      g_num_ports           => g_owr_num_ports,
+      g_num_ports           => 1,
      g_ow_btp_normal       => "5.0",
      g_ow_btp_overdrive    => "1.0"
    )
@@ -200,9 +210,11 @@ begin
      slave_o => slave_o(2),
      desc_o  => open,
-      owr_pwren_o => owr_pwren_o,
+      owr_en_o => owr_en_slv,
-      owr_en_o    => owr_en_o,
+      owr_i    => owr_in_slv
-      owr_i       => owr_i
    );
+  owr_in_slv(0) <= owr_i;
+  owr_en_o      <= owr_en_slv(0);
 end struct;