serial_dac856x.vhd: set gain

9a6ced7b · Tristan Gingold · eefe0fce · 9a6ced7b
Commit 9a6ced7b authored Oct 25, 2023 by Tristan Gingold
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serial_dac856x.vhd modules/wr_dacs/serial_dac856x.vhd +6 -1

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--- a/modules/wr_dacs/serial_dac856x.vhd
+++ b/modules/wr_dacs/serial_dac856x.vhd
@@ -28,7 +28,7 @@ end serial_dac856x;

 architecture behav of serial_dac856x is
  --  Initialization state machine.
-  type t_state is (S_WAIT, S_CMD_SYNC, S_CMD_REF, S_DONE);
+  type t_state is (S_WAIT, S_CMD_SYNC, S_CMD_REF, S_CMD_GAIN, S_DONE);
  signal state : t_state;

  --  Serial clock generation.
@@ -138,6 +138,11 @@ begin
              --  Set reference
              buf <= "XX" & "111" & "XXX" & "XXXXXXXXXXXXXXX" & g_internal_ref;
              busy <= '1';
+              state <= S_CMD_GAIN;
+            when S_CMD_GAIN =>
+              --  Set gain (1 on both channels)
+              buf <= "XX" & "010" & "XXX" & "XXXXXXXXXXXXXX" & "11";
+              busy <= '1';
              state <= S_DONE;
            when S_DONE =>
              --  Choose (with implicit priority the new data to be transmitted).