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White Rabbit core collection
Commit 99f1c964 authored by Peter Jansweijer's avatar Peter Jansweijer
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move pll_62m5_500m, gen_10MHz, even_odd_det and probe_10mhz to spec7 board level

parent 4839d8bf
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Showing with 111 additions and 91 deletions
board/spec7/Manifest.py
View file @ 99f1c964
files = [
"even_odd_det.vhd",
"gen_10mhz.vhd",
"pll_62m5_500m.vhd",
"probe_10mhz.vhd",
"wr_spec7_pkg.vhd",
"wrc_board_spec7.vhd",
"xwrc_board_spec7.vhd",
......
board/spec7/wr_spec7_pkg.vhd
View file @ 99f1c964
......@@ -151,6 +151,8 @@ package wr_spec7_pkg is
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
aligned_10mhz_o : out std_logic;
clk_10m_out_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_spec7;
......
board/spec7/wrc_board_spec7.vhd
View file @ 99f1c964
......@@ -301,15 +301,17 @@ entity wrc_board_spec7 is
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS, 10 MHz output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
aligned_10mhz_o : out std_logic;
clk_10m_out_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
link_ok_o : out std_logic
);
end entity wrc_board_spec7;
......
board/spec7/xwrc_board_spec7.vhd
View file @ 99f1c964
......@@ -256,15 +256,17 @@ entity xwrc_board_spec7 is
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS, 10 MHz output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
aligned_10mhz_o : out std_logic;
clk_10m_out_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
link_ok_o : out std_logic
);
end entity xwrc_board_spec7;
......@@ -295,8 +297,14 @@ architecture struct of xwrc_board_spec7 is
signal pll_clk_sel : std_logic;
signal pll_clk_select : std_logic;
signal clk_500m : std_logic;
signal pps_out : std_logic;
signal clk_10m_out : std_logic;
signal aligned_10mhz : std_logic;
-- Reset logic
signal rst_62m5_n : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_62m5_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
......@@ -345,6 +353,24 @@ architecture struct of xwrc_board_spec7 is
constant c_num_gpio_pins : integer := 17;
signal gpio_out, gpio_in, gpio_oen : std_logic_vector(c_num_gpio_pins-1 downto 0);
component pll_62m5_500m is
port (
areset_n_i : in std_logic;
clk_62m5_pllref_i : in std_logic;
clk_500m_o : out std_logic;
pll_500m_locked_o : out std_logic
);
end component pll_62m5_500m;
component gen_10mhz is
port (
clk_500m_i : in std_logic;
rst_n_i : in std_logic;
pps_i : in std_logic;
clk_10mhz_o : out std_logic
);
end component gen_10mhz;
component even_odd_det is
port (
rst_n_i : in std_logic;
......@@ -359,6 +385,16 @@ architecture struct of xwrc_board_spec7 is
);
end component even_odd_det;
component probe_10mhz is
port (
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_10mhz_a_i : in std_logic;
clk_10mhz_b_i : in std_logic;
aligned_o : out std_logic
);
end component probe_10mhz;
begin -- architecture struct
-----------------------------------------------------------------------------
......@@ -405,9 +441,30 @@ begin -- architecture struct
I => clk_125m_gtx_buf,
O => clk_ref_125m);
------------------------------------------------------------------------------
-- 10MHz output generation
------------------------------------------------------------------------------
-- A 500 MHz reference clock is necessary since 10 MHz = 50 ns '1', 50 ns '0'
-- and 50 ns is divisible by 2 ns (not by 8 or 4 ns!) hence 500 MHz.
cmp_pll_62m5_500m: pll_62m5_500m
port map (
areset_n_i => rst_ref_62m5_n,
clk_62m5_pllref_i => clk_ref_62m5,
clk_500m_o => clk_500m,
pll_500m_locked_o => open
);
cmp_gen_10mhz: gen_10mhz
port map (
clk_500m_i => clk_500m,
rst_n_i => rst_ref_62m5_n,
pps_i => pps_out,
clk_10mhz_o => clk_10m_out
);
cmp_even_odd_det: even_odd_det
port map (
rst_n_i => areset_n_i,
rst_n_i => areset_n_i,
clk_ref_i => clk_ref_125m,
clk_10m_ext_i => clk_10m_ext_i,
clk_sys_62m5_i => clk_sys_62m5,
......@@ -417,6 +474,17 @@ begin -- architecture struct
sync_done_o => sync_done,
sync_o => sync_clk_ref_62m5);
cmp_probe_10mhz: probe_10mhz
port map (
rst_n_i => rst_ref_62m5_n,
clk_ref_i => clk_ref_62m5,
clk_10mhz_a_i => clk_10m_ext,
clk_10mhz_b_i => clk_10m_out,
aligned_o => aligned_10mhz);
aligned_10mhz_o <= aligned_10mhz;
clk_10m_out_o <= clk_10m_out;
---------------------------------------------------------------------------
-- PLL sync signal synchronizes the LTC6950 but it waits for the proper
-- 10 MHz cycle before re-enabling the clock. This means that it shifts
......@@ -613,10 +681,11 @@ begin -- architecture struct
rstn_o => rstlogic_rst_out);
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n <= rstlogic_rst_out(0);
rst_sys_62m5_n <= rstlogic_rst_out(0);
rst_ref_62m5_n <= rstlogic_rst_out(1);
rst_sys_62m5_n_o <= rst_62m5_n;
rst_ref_62m5_n_o <= rstlogic_rst_out(1);
rst_sys_62m5_n_o <= rst_sys_62m5_n;
rst_ref_62m5_n_o <= rst_ref_62m5_n;
-----------------------------------------------------------------------------
-- 2x SPI DAC
......@@ -630,7 +699,7 @@ begin -- architecture struct
g_sclk_polarity => 0)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
rst_n_i => rst_sys_62m5_n,
value_i => dac_dmtd_data,
cs_sel_i => "1",
load_i => dac_dmtd_load,
......@@ -647,7 +716,7 @@ begin -- architecture struct
g_sclk_polarity => 0)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
rst_n_i => rst_sys_62m5_n,
value_i => dac_refclk_data,
cs_sel_i => "1",
load_i => dac_refclk_load,
......@@ -700,7 +769,7 @@ begin -- architecture struct
clk_ext_stopped_i => ext_ref_mul_stopped,
clk_ext_rst_o => ext_ref_rst,
pps_ext_i => pps_ext_i,
rst_n_i => rst_62m5_n,
rst_n_i => rst_sys_62m5_n,
dac_hpll_load_p1_o => dac_dmtd_load,
dac_hpll_data_o => dac_dmtd_data,
dac_dpll_load_p1_o => dac_refclk_load,
......@@ -766,10 +835,12 @@ begin -- architecture struct
led_link_o => led_link_o,
btn1_i => btn1_i,
btn2_i => btn2_i,
pps_p_o => pps_p_o,
pps_p_o => pps_out,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o);
pps_p_o <= pps_out;
cmp_wb_spec7_con : xwb_crossbar
generic map (
g_num_masters => c_cnx_slave_ports,
......@@ -779,7 +850,7 @@ begin -- architecture struct
g_mask => c_cfg_base_mask)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
......@@ -793,7 +864,7 @@ begin -- architecture struct
g_with_builtin_tristates => false)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_62m5_n,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_slave_gpio),
slave_o => cnx_master_in(c_slave_gpio),
gpio_out_o => gpio_out,
......@@ -821,7 +892,8 @@ begin -- architecture struct
eeprom_sda <= '0' when (gpio_out(12) = '0') else 'Z';
gpio_in(12) <= eeprom_sda;
gpio_in(13) <= even_odd_n; -- 10MHz/1PPS phase w.r.t. clk_ref_125m
-- gpio_in(13) <= even_odd_n; -- 10MHz/1PPS phase w.r.t. clk_ref_125m
gpio_in(13) <= aligned_10mhz;
gpio_in(14) <= sync_done;
-- AUXiliary I2C tri-states
......
top/spec7_ref_design/Manifest.py
View file @ 99f1c964
fetchto = "../../ip_cores"
files = [
"gen_10mhz.vhd",
"pll_62m5_500m.vhd",
"probe_10mhz.vhd",
"spec7_wr_ref_top.vhd",
"spec7_wr_ref_top.xdc",
"spec7_wr_ref_top.bmm",
......
top/spec7_ref_design/spec7_wr_ref_top.vhd
View file @ 99f1c964
......@@ -160,7 +160,7 @@ entity spec7_wr_ref_top is
wdog_n_o : out std_logic;
-- blink 1-PPS.
led_pps_o : out std_logic;
led_pps_o : out std_logic;
aligned_10mhz_o : out std_logic;
---------------------------------------------------------------------------
-- EEPROM interface
......@@ -375,7 +375,6 @@ architecture top of spec7_wr_ref_top is
signal clk_ref_62m5 : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_10m_out : std_logic;
signal clk_500m : std_logic;
signal clk_ext_10m : std_logic;
-- DAC signals for reference clock
......@@ -411,34 +410,6 @@ architecture top of spec7_wr_ref_top is
--PCIe
signal pci_clk : std_logic;
component pll_62m5_500m is
port (
areset_n_i : in std_logic;
clk_62m5_pllref_i : in std_logic;
clk_500m_o : out std_logic;
pll_500m_locked_o : out std_logic
);
end component pll_62m5_500m;
component gen_10mhz is
port (
clk_500m_i : in std_logic;
rst_n_i : in std_logic;
pps_i : in std_logic;
clk_10mhz_o : out std_logic
);
end component gen_10mhz;
component probe_10mhz is
port (
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_10mhz_a_i : in std_logic;
clk_10mhz_b_i : in std_logic;
aligned_o : out std_logic
);
end component probe_10mhz;
begin -- architecture top
-- Never trigger PS_POR or PROGRAM_B
......@@ -619,9 +590,11 @@ AXI2WB : xwb_axi4lite_bridge
pps_ext_i => wrc_pps_in,
pps_p_o => wrc_pps_out,
pps_led_o => wrc_pps_led,
aligned_10mhz_o => aligned_10mhz_o,
clk_10m_out_o => clk_10m_out,
led_link_o => led_link_o,
led_act_o => led_act_o);
-- DAC signals for on board reference clock
dac_refclk_sclk_o <= dac_refclk_sclk_int_o;
dac_refclk_din_o <= dac_refclk_din_int_o;
......@@ -669,35 +642,6 @@ AXI2WB : xwb_axi4lite_bridge
end if;
end process;
------------------------------------------------------------------------------
-- 10MHz output generation
------------------------------------------------------------------------------
-- A 500 MHz reference clock is necessary since 10 MHz = 50 ns '1', 50 ns '0'
-- and 50 ns is divisible by 2 ns (not by 8 or 4 ns!) hence 500 MHz.
cmp_pll_62m5_500m: pll_62m5_500m
port map (
areset_n_i => rst_ref_62m5_n,
clk_62m5_pllref_i => clk_ref_62m5,
clk_500m_o => clk_500m,
pll_500m_locked_o => open
);
cmp_gen_10mhz: gen_10mhz
port map (
clk_500m_i => clk_500m,
rst_n_i => rst_ref_62m5_n,
pps_i => wrc_pps_out,
clk_10mhz_o => clk_10m_out
);
cmp_probe_10mhz: probe_10mhz
port map (
rst_n_i => rst_ref_62m5_n,
clk_ref_i => clk_ref_62m5,
clk_10mhz_a_i => clk_ext_10m,
clk_10mhz_b_i => clk_10m_out,
aligned_o => aligned_10mhz_o);
cmp_obuf_be_10mhz_out : OBUFDS
port map (
I => clk_10m_out,
......
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