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White Rabbit core collection
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White Rabbit core collection
Commits
9810ef9a
Commit
9810ef9a
authored
Aug 17, 2018
by
Dimitris Lampridis
2
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hdl: use dual reset async fifos and pulse synchronizers to help with meeting timing
parent
6fd625d4
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4 changed files
with
22 additions
and
19 deletions
+22
-19
dmtd_with_deglitcher.vhd
modules/timing/dmtd_with_deglitcher.vhd
+9
-8
ep_clock_alignment_fifo.vhd
modules/wr_endpoint/ep_clock_alignment_fifo.vhd
+4
-3
ep_packet_filter.vhd
modules/wr_endpoint/ep_packet_filter.vhd
+8
-7
ep_timestamping_unit.vhd
modules/wr_endpoint/ep_timestamping_unit.vhd
+1
-1
No files found.
modules/timing/dmtd_with_deglitcher.vhd
View file @
9810ef9a
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 201
4-07-15
-- Last update: 201
8-08-03
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
...
...
@@ -164,11 +164,12 @@ begin -- rtl
data_i
=>
resync_p_a_i
,
synced_o
=>
resync_p_dmtd
);
U_Sync_Start_Pulse
:
gc_pulse_synchronizer
U_Sync_Start_Pulse
:
gc_pulse_synchronizer
2
port
map
(
clk_in_i
=>
clk_sys_i
,
rst_in_n_i
=>
rst_n_sysclk_i
,
clk_out_i
=>
clk_dmtd_i
,
rst_
n_i
=>
rst_n_dmtdclk_i
,
rst_
out_n_i
=>
rst_n_dmtdclk_i
,
d_ready_o
=>
open
,
d_p_i
=>
resync_start_p_i
,
q_p_o
=>
resync_start_p_dmtd
);
...
...
modules/wr_endpoint/ep_clock_alignment_fifo.vhd
View file @
9810ef9a
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 201
2-08-28
-- Last update: 201
8-08-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -84,7 +84,7 @@ begin
f_pack_fifo_contents
(
fab_i
,
fifo_in
,
fifo_we
,
false
);
-- Clock adjustment FIFO
U_FIFO
:
generic_async_fifo
U_FIFO
:
generic_async_fifo
_dual_rst
generic
map
(
g_data_width
=>
18
,
g_size
=>
g_size
,
...
...
@@ -92,12 +92,13 @@ begin
g_almost_full_threshold
=>
g_almostfull_threshold
)
port
map
(
rst_
n_i
=>
rst_n_wr_i
,
rst_
wr_n_i
=>
rst_n_wr_i
,
clk_wr_i
=>
clk_wr_i
,
d_i
=>
fifo_in
,
we_i
=>
fifo_we
,
wr_full_o
=>
full_o
,
wr_almost_full_o
=>
almostfull_o
,
rst_rd_n_i
=>
rst_n_rd_i
,
clk_rd_i
=>
clk_rd_i
,
q_o
=>
fifo_out
,
rd_i
=>
rx_rdreq
,
...
...
modules/wr_endpoint/ep_packet_filter.vhd
View file @
9810ef9a
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 201
7-02-02
-- Last update: 201
8-08-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -360,11 +360,12 @@ begin -- behavioral
end
if
;
end
process
;
U_Sync_Done
:
gc_pulse_synchronizer
U_Sync_Done
:
gc_pulse_synchronizer
2
port
map
(
clk_in_i
=>
clk_rx_i
,
rst_in_n_i
=>
rst_n_rx_i
,
clk_out_i
=>
clk_sys_i
,
rst_
n_i
=>
rst_n_rx
_i
,
rst_
out_n_i
=>
rst_n_sys
_i
,
d_p_i
=>
done_int
,
q_p_o
=>
done_o
);
...
...
modules/wr_endpoint/ep_timestamping_unit.vhd
View file @
9810ef9a
...
...
@@ -7,7 +7,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 201
7-02
-03
-- Last update: 201
8-08
-03
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
...
...
Grzegorz Daniluk
@greg.d
mentioned in commit
93d49e1f
·
Feb 14, 2019
mentioned in commit
93d49e1f
mentioned in commit 93d49e1fab0dc6bee91ce48646d3016bcd2f3fea
Toggle commit list
Dimitris Lampridis
@dlampridis
mentioned in commit
b6dfc740
·
Feb 14, 2019
mentioned in commit
b6dfc740
mentioned in commit b6dfc740f4fe23564972ffefcc1caee8ee820b2b
Toggle commit list
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