wr_minic: added testbench (interfaced directly with WBPacketSource/Sink)

9750bc52 · Tomasz Wlostowski · 879d4875 · 9750bc52 · 9750bc52 · 9750bc52
Commit 9750bc52 authored Oct 25, 2011 by Tomasz Wlostowski
Showing with 448 additions and 0 deletions

Manifest.py testbench/wr_minic/Manifest.py +9 -0

main.sv testbench/wr_minic/main.sv +295 -0

run.do testbench/wr_minic/run.do +10 -0

wave.do testbench/wr_minic/wave.do +134 -0

No files found.
--- a/testbench/wr_minic/Manifest.py
+++ b/testbench/wr_minic/Manifest.py
+action = "simulation"
+files = "main.sv"
+#fetchto = "../../ip_cores"
+
+vlog_opt="+incdir+../../sim"
+
+modules ={"local" : ["../../ip_cores/general-cores",
+                     "../../modules/wr_endpoint", 
+                     "../../modules/wr_mini_nic" ] };
--- a/testbench/wr_minic/main.sv
+++ b/testbench/wr_minic/main.sv
+`include "if_wb_master.svh"
+`include "if_wb_slave.svh"
+`include "wb_packet_source.svh"
+`include "wb_packet_sink.svh"
+
+`include "simdrv_minic.svh"
+`include "ep2ep_wrapper.svh"
+
+
+module main;
+
+   reg clk_sys = 1'b0;
+   reg rst_n = 1'b0;
+
+   always #5ns clk_sys <= ~clk_sys;
+   initial begin
+      repeat(3) @(posedge clk_sys);
+      rst_n <= 1'b1;
+   end
+
+   IWishboneMaster 
+     #(
+       .g_data_width(16),
+       .g_addr_width(2))
+   U_wrf_source
+     (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)
+      );
+
+   IWishboneSlave
+     #(
+       .g_data_width(16),
+       .g_addr_width(2))
+   U_wrf_sink
+     (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)
+      );
+   
+   IWishboneMaster 
+     #(
+       .g_data_width(32),
+       .g_addr_width(32))
+   U_sys_bus_master
+     (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)
+      );
+
+
+   IWishboneMaster 
+     #(
+       .g_data_width(32),
+       .g_addr_width(16))
+   U_pmem_bus_master
+     (
+      .clk_i(clk_sys),
+      .rst_n_i(rst_n)
+      );
+
+
+
+   wire minic_irq;
+   wire [31:0] pmem_wr_data, pmem_rd_data;
+   wire [13:0] pmem_addr;
+   wire pmem_wr;
+   
+   wr_mini_nic DUT 
+     (
+      .clk_sys_i (clk_sys),
+      .rst_n_i   (rst_n),
+
+      .mem_data_o (pmem_wr_data),
+      .mem_addr_o (pmem_addr),
+      .mem_data_i (pmem_rd_data),
+      .mem_wr_o   (pmem_wr),
+
+      .src_dat_o  (U_wrf_sink.dat_i),
+      .src_adr_o  (U_wrf_sink.adr),
+      .src_sel_o  (U_wrf_sink.sel),
+      .src_cyc_o  (U_wrf_sink.cyc),
+      .src_stb_o  (U_wrf_sink.stb),
+      .src_we_o   (U_wrf_sink.we),
+      .src_stall_i(U_wrf_sink.stall),
+      .src_err_i  (U_wrf_sink.err),
+      .src_ack_i  (U_wrf_sink.ack),
+
+      .snk_dat_i  (U_wrf_source.dat_o), 
+      .snk_adr_i  (U_wrf_source.adr),
+      .snk_sel_i  (U_wrf_source.sel),
+      .snk_cyc_i  (U_wrf_source.cyc),
+      .snk_stb_i  (U_wrf_source.stb), 
+      .snk_we_i    (U_wrf_source.we),
+      .snk_stall_o (U_wrf_source.stall),
+      .snk_err_o   (U_wrf_source.err),
+      .snk_ack_o   (U_wrf_source.ack),
+
+      .txtsu_port_id_i  (5'b0),
+      .txtsu_frame_id_i (16'b0),
+      .txtsu_tsval_i   (32'b0),
+      .txtsu_valid_i   (1'b0),
+      .txtsu_ack_o     (),
+
+
+      .wb_cyc_i   (U_sys_bus_master.cyc),
+      .wb_stb_i   (U_sys_bus_master.stb),
+      .wb_we_i    (U_sys_bus_master.we),
+      .wb_sel_i   (U_sys_bus_master.sel),
+      .wb_adr_i   (U_sys_bus_master.adr),
+      .wb_dat_i   (U_sys_bus_master.dat_o),
+      .wb_dat_o   (U_sys_bus_master.dat_i),
+      .wb_ack_o   (U_sys_bus_master.ack),
+      .wb_stall_o (U_sys_bus_master.stall),
+      .wb_irq_o   (minic_irq)
+      );
+
+   minic_packet_buffer PBUF
+     (
+      .clk_sys_i (clk_sys),
+      .rst_n_i  (rst_n),
+
+      .minic_addr_i (pmem_addr),
+      .minic_data_i (pmem_wr_data),
+      .minic_wr_i   (pmem_wr),
+      .minic_data_o (pmem_rd_data),
+      
+      .wb_cyc_i   (U_pmem_bus_master.cyc),
+      .wb_stb_i   (U_pmem_bus_master.stb),
+      .wb_we_i    (U_pmem_bus_master.we),
+      .wb_addr_i   (U_pmem_bus_master.adr[13:0]),
+      .wb_data_i   (U_pmem_bus_master.dat_o),
+      .wb_data_o   (U_pmem_bus_master.dat_i),
+      .wb_ack_o   (U_pmem_bus_master.ack)
+    );
+
+   
+   CSimDrv_Minic minic;
+
+
+
+   task test_tx_path(int n_packets, CSimDrv_Minic minic, WBPacketSink sink);
+      EthPacketGenerator gen = new;
+      EthPacket pkt, tmpl;
+      EthPacket txed[$];
+      int i;
+
+       tmpl           = new;
+      tmpl.src       = '{1,2,3,4,5,6};
+      tmpl.dst       = '{10,11,12,13,14,15};
+      tmpl.has_smac  = 1;
+      tmpl.is_q      = 0;
+      
+      gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE | EthPacketGenerator::TX_OOB | EthPacketGenerator::EVEN_LENGTH) ;
+      gen.set_template(tmpl);
+      gen.set_size(60,1500);
+      
+      for(i=0;i<n_packets;i++)
+        begin
+           pkt  = gen.gen();
+           minic.send(pkt);
+           txed.push_back(pkt);
+        end
+
+      fork
+         forever
+           begin
+              minic.run();
+              #1;
+           end
+
+         forever
+           begin
+            if(sink.poll())
+              begin
+                 EthPacket rxp, sent;
+                 sink.recv(rxp);
+                 sent  = txed.pop_front();
+                 if(!sent.equal(rxp, EthPacket::CMP_OOB))
+                   begin
+                      sent.dump();
+                      rxp.dump();
+                      $stop;
+                   end
+              end
+              #1;
+         end
+      join
+
+   endtask
+   
+   
+   
+   initial begin
+      CWishboneAccessor sys_bus, pmem_bus;     
+      WBPacketSource src  = new(U_wrf_source.get_accessor());
+      WBPacketSink sink   = new(U_wrf_sink.get_accessor()); 
+      EthPacketGenerator gen = new;
+      EthPacket pkt, tmpl;
+      EthPacket txed[$];
+      int i;
+
+    
+      
+
+   
+      
+      
+      @(posedge rst_n);
+      @(posedge clk_sys);
+ 
+      sys_bus                                 = U_sys_bus_master.get_accessor();
+      sys_bus.set_mode(CLASSIC);
+      pmem_bus                                 = U_pmem_bus_master.get_accessor();
+      pmem_bus.set_mode(CLASSIC);
+
+      minic  = new('h10000, sys_bus, 0, pmem_bus, 0);
+      minic.init();
+      
+
+     
+         tmpl           = new;
+      tmpl.src       = '{1,2,3,4,5,6};
+      tmpl.dst       = '{10,11,12,13,14,15};
+      tmpl.has_smac  = 1;
+      tmpl.is_q      = 0;
+      
+      gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /*| EthPacketGenerator::RX_OOB*/) ;
+      gen.set_template(tmpl);
+      gen.set_size(60,1500);
+
+
+      fork
+         forever
+           begin
+              minic.run();
+      
+
+              if(minic.poll())
+              begin
+                 EthPacket rxp, sent;
+                 minic.recv(rxp);
+                 sent  = txed.pop_front();
+                 if(!sent.equal(rxp, EthPacket::CMP_OOB))
+                   begin
+                      sent.dump();
+                      rxp.dump();
+                      $stop;
+                   end
+
+/* -----\/----- EXCLUDED -----\/-----
+                 else
+                   rxp.dump();
+ -----/\----- EXCLUDED -----/\----- */
+                 
+              end
+
+              #1;
+              end
+
+//         forever
+           begin
+              for(i=0;i<100;i++)
+                begin
+                   pkt  = gen.gen();
+                   src.send(pkt);
+                   txed.push_back(pkt);
+                end
+
+              
+           end
+         
+    //          #1;
+              
+  //         end // forever begin
+
+         
+         
+         
+              
+
+      join      
+
+         
+      
+        
+      
+   end // initial begin
+
+   
+   
+endmodule // main
+
+
+
--- a/testbench/wr_minic/run.do
+++ b/testbench/wr_minic/run.do
+vlog -sv main.sv +incdir+"." +incdir+../../sim
+make -f Makefile
+vsim -L unisim -t 10fs work.main -voptargs="+acc"
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+radix -hexadecimal
+run 250us
+wave zoomfull
+radix -hexadecimal
--- a/testbench/wr_minic/wave.do
+++ b/testbench/wr_minic/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/g_interface_mode
+add wave -noupdate /main/DUT/g_address_granularity
+add wave -noupdate /main/DUT/g_memsize_log2
+add wave -noupdate /main/DUT/g_buffer_little_endian
+add wave -noupdate /main/DUT/clk_sys_i
+add wave -noupdate /main/DUT/rst_n_i
+add wave -noupdate /main/DUT/mem_data_o
+add wave -noupdate /main/DUT/mem_addr_o
+add wave -noupdate /main/DUT/mem_data_i
+add wave -noupdate /main/DUT/mem_wr_o
+add wave -noupdate /main/DUT/src_dat_o
+add wave -noupdate /main/DUT/src_adr_o
+add wave -noupdate /main/DUT/src_sel_o
+add wave -noupdate /main/DUT/src_cyc_o
+add wave -noupdate /main/DUT/src_stb_o
+add wave -noupdate /main/DUT/src_we_o
+add wave -noupdate /main/DUT/src_stall_i
+add wave -noupdate /main/DUT/src_err_i
+add wave -noupdate /main/DUT/src_ack_i
+add wave -noupdate /main/DUT/snk_dat_i
+add wave -noupdate /main/DUT/snk_adr_i
+add wave -noupdate /main/DUT/snk_sel_i
+add wave -noupdate /main/DUT/snk_cyc_i
+add wave -noupdate /main/DUT/snk_stb_i
+add wave -noupdate /main/DUT/snk_we_i
+add wave -noupdate /main/DUT/snk_stall_o
+add wave -noupdate /main/DUT/snk_err_o
+add wave -noupdate /main/DUT/snk_ack_o
+add wave -noupdate /main/DUT/txtsu_port_id_i
+add wave -noupdate /main/DUT/txtsu_frame_id_i
+add wave -noupdate /main/DUT/txtsu_tsval_i
+add wave -noupdate /main/DUT/txtsu_valid_i
+add wave -noupdate /main/DUT/txtsu_ack_o
+add wave -noupdate /main/DUT/wb_cyc_i
+add wave -noupdate /main/DUT/wb_stb_i
+add wave -noupdate /main/DUT/wb_we_i
+add wave -noupdate /main/DUT/wb_sel_i
+add wave -noupdate /main/DUT/wb_adr_i
+add wave -noupdate /main/DUT/wb_dat_i
+add wave -noupdate /main/DUT/wb_dat_o
+add wave -noupdate /main/DUT/wb_ack_o
+add wave -noupdate /main/DUT/wb_stall_o
+add wave -noupdate /main/DUT/wb_irq_o
+add wave -noupdate /main/DUT/src_cyc_int
+add wave -noupdate /main/DUT/src_stb_int
+add wave -noupdate /main/DUT/snk_stall_int
+add wave -noupdate /main/DUT/ntx_mem_d
+add wave -noupdate /main/DUT/ntx_mem_a
+add wave -noupdate /main/DUT/nrx_mem_d
+add wave -noupdate /main/DUT/nrx_mux_d
+add wave -noupdate /main/DUT/nrx_mem_a
+add wave -noupdate /main/DUT/nrx_mem_wr
+add wave -noupdate /main/DUT/mem_arb_rx
+add wave -noupdate /main/DUT/mem_arb_tx
+add wave -noupdate /main/DUT/ntx_status_reg
+add wave -noupdate /main/DUT/ntx_data_reg
+add wave -noupdate /main/DUT/ntx_cntr_is_zero
+add wave -noupdate /main/DUT/ntx_cntr_is_one
+add wave -noupdate /main/DUT/ntx_timeout_is_zero
+add wave -noupdate /main/DUT/ntx_cntr
+add wave -noupdate /main/DUT/ntx_timeout
+add wave -noupdate /main/DUT/ntx_ack_count
+add wave -noupdate /main/DUT/ntx_has_oob
+add wave -noupdate /main/DUT/ntx_state
+add wave -noupdate /main/DUT/ntx_start_delayed
+add wave -noupdate /main/DUT/ntx_size_odd
+add wave -noupdate /main/DUT/ntx_oob_reg
+add wave -noupdate /main/DUT/nrx_state
+add wave -noupdate /main/DUT/nrx_avail
+add wave -noupdate /main/DUT/nrx_toggle
+add wave -noupdate /main/DUT/nrx_oob_reg
+add wave -noupdate /main/DUT/nrx_status_reg
+add wave -noupdate /main/DUT/nrx_error
+add wave -noupdate /main/DUT/nrx_mem_a_saved
+add wave -noupdate /main/DUT/nrx_has_oob
+add wave -noupdate /main/DUT/nrx_bytesel
+add wave -noupdate /main/DUT/nrx_size
+add wave -noupdate /main/DUT/nrx_rdreg
+add wave -noupdate /main/DUT/nrx_buf_full
+add wave -noupdate /main/DUT/nrx_stall_mask
+add wave -noupdate /main/DUT/nrx_valid
+add wave -noupdate /main/DUT/nrx_done
+add wave -noupdate /main/DUT/nrx_drop
+add wave -noupdate /main/DUT/nrx_stat_error
+add wave -noupdate /main/DUT/regs_in
+add wave -noupdate /main/DUT/regs_out
+add wave -noupdate /main/DUT/wb_in
+add wave -noupdate /main/DUT/wb_out
+add wave -noupdate /main/DUT/irq_tx
+add wave -noupdate /main/DUT/irq_rx_ack
+add wave -noupdate /main/DUT/irq_rx
+add wave -noupdate /main/DUT/nrx_newpacket
+add wave -noupdate /main/DUT/nrx_newpacket_d0
+add wave -noupdate /main/DUT/irq_txts
+add wave -noupdate /main/DUT/irq_tx_ack
+add wave -noupdate /main/DUT/irq_tx_mask
+add wave -noupdate /main/DUT/txtsu_ack_int
+add wave -noupdate /main/DUT/nrx_status_hp
+add wave -noupdate /main/DUT/nrx_status_smac
+add wave -noupdate /main/DUT/nrx_status_crc
+add wave -noupdate /main/DUT/nrx_status_err
+add wave -noupdate /main/DUT/nrx_status_tagme
+add wave -noupdate /main/DUT/nrx_status_class
+add wave -noupdate /main/DUT/ntx_status_hp
+add wave -noupdate /main/DUT/ntx_status_smac
+add wave -noupdate /main/DUT/ntx_status_crc
+add wave -noupdate /main/DUT/ntx_status_err
+add wave -noupdate /main/DUT/ntx_status_tagme
+add wave -noupdate /main/DUT/ntx_status_class
+add wave -noupdate /main/DUT/ntx_desc_has_src_mac
+add wave -noupdate /main/DUT/ntx_desc_802_1q
+add wave -noupdate /main/DUT/ntx_desc_with_oob
+add wave -noupdate /main/DUT/ntx_desc_valid
+add wave -noupdate /main/DUT/ntx_desc_oob
+add wave -noupdate /main/DUT/ntx_desc_size
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {90685000000 fs} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {90556826170 fs} {90813173830 fs}