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White Rabbit core collection
Commit 95757b8c authored by José López Jiménez's avatar José López Jiménez
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Updated softpll regs for holdover board support

parent 3add48fc
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Showing with 133 additions and 3 deletions
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @ 95757b8c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu May 28 20:37:18 2020
-- Created : Mon Jul 27 16:35:16 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -58,6 +58,10 @@ signal spll_trr_in_int : std_logic_vector(31 downto 0);
signal spll_trr_out_int : std_logic_vector(31 downto 0);
signal spll_trr_rdreq_int : std_logic ;
signal spll_trr_rdreq_int_d0 : std_logic ;
signal spll_ho_cr_ho_active_int : std_logic ;
signal spll_ho_cr_lrn_active_int : std_logic ;
signal spll_ho_cr_func_sel_int : std_logic_vector(3 downto 0);
signal spll_ho_rate_int : std_logic_vector(31 downto 0);
signal eic_idr_int : std_logic_vector(0 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(0 downto 0);
......@@ -110,6 +114,10 @@ begin
spll_deglitch_thr_int <= "0000000000000000";
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
spll_ho_cr_ho_active_int <= '0';
spll_ho_cr_lrn_active_int <= '0';
spll_ho_cr_func_sel_int <= "0000";
spll_ho_rate_int <= "00000000000000000000000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -524,6 +532,50 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010101" =>
if (wb_we_i = '1') then
spll_ho_cr_ho_active_int <= wrdata_reg(0);
spll_ho_cr_lrn_active_int <= wrdata_reg(4);
spll_ho_cr_func_sel_int <= wrdata_reg(11 downto 8);
end if;
rddata_reg(0) <= spll_ho_cr_ho_active_int;
rddata_reg(4) <= spll_ho_cr_lrn_active_int;
rddata_reg(11 downto 8) <= spll_ho_cr_func_sel_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010110" =>
if (wb_we_i = '1') then
spll_ho_rate_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= spll_ho_rate_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
......@@ -900,6 +952,14 @@ begin
rd_data_o => spll_trr_out_int
);
-- Holdover active
regs_o.ho_cr_ho_active_o <= spll_ho_cr_ho_active_int;
-- Learning active
regs_o.ho_cr_lrn_active_o <= spll_ho_cr_lrn_active_int;
-- Holdover function select
regs_o.ho_cr_func_sel_o <= spll_ho_cr_func_sel_int;
-- Sample rate setting
regs_o.ho_rate_o <= spll_ho_rate_int;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt enable register
......
modules/wr_softpll_ng/spll_wb_slave.wb
View file @ 95757b8c
......@@ -418,6 +418,60 @@ peripheral {
prefix = "TAG";
trigger = LEVEL_1;
};
reg {
name = "Holdover Control Register";
prefix = "HO_CR";
field {
name = "Holdover active";
prefix = "HO_ACTIVE";
description = "1: holdover is active\
0: holdover is not active";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Learning active";
prefix = "LRN_ACTIVE";
align = 4;
description = "1: learning is active (corrections from WR SoftPLL are being saved into a circular buffer)\
0: learning is not active";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Holdover function select";
prefix = "FUNC_SEL";
align = 8;
description = "Select one of many different holdover approaches at runtime.";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "HO buffer sample rate register";
description = "Register controlling the sample rate of the available data circular buffer";
prefix = "HO_RATE";
field {
name = "Sample rate setting";
description = "The holdover circular buffer will be fed with 1 out of [RATE] data points generated by the SoftPLL";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ 95757b8c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Thu May 28 20:37:18 2020
-- Created : Mon Jul 27 16:35:16 2020
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -114,6 +114,10 @@ package spll_wbgen2_pkg is
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
trr_wr_full_o : std_logic;
trr_wr_empty_o : std_logic;
ho_cr_ho_active_o : std_logic;
ho_cr_lrn_active_o : std_logic;
ho_cr_func_sel_o : std_logic_vector(3 downto 0);
ho_rate_o : std_logic_vector(31 downto 0);
end record;
constant c_spll_out_registers_init_value: t_spll_out_registers := (
......@@ -149,7 +153,11 @@ package spll_wbgen2_pkg is
dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'),
trr_wr_full_o => '0',
trr_wr_empty_o => '0'
trr_wr_empty_o => '0',
ho_cr_ho_active_o => '0',
ho_cr_lrn_active_o => '0',
ho_cr_func_sel_o => (others => '0'),
ho_rate_o => (others => '0')
);
function "or" (left, right: t_spll_in_registers) return t_spll_in_registers;
......
sim/softpll_regs_ng.vh
View file @ 95757b8c
......@@ -62,6 +62,14 @@
`define SPLL_DFR_SPLL_VALUE 32'h7fffffff
`define SPLL_DFR_SPLL_EOS_OFFSET 31
`define SPLL_DFR_SPLL_EOS 32'h80000000
`define ADDR_SPLL_HO_CR 8'h54
`define SPLL_HO_CR_HO_ACTIVE_OFFSET 0
`define SPLL_HO_CR_HO_ACTIVE 32'h00000001
`define SPLL_HO_CR_LRN_ACTIVE_OFFSET 4
`define SPLL_HO_CR_LRN_ACTIVE 32'h00000010
`define SPLL_HO_CR_FUNC_SEL_OFFSET 8
`define SPLL_HO_CR_FUNC_SEL 32'h00000f00
`define ADDR_SPLL_HO_RATE 8'h58
`define ADDR_SPLL_EIC_IDR 8'h60
`define SPLL_EIC_IDR_TAG_OFFSET 0
`define SPLL_EIC_IDR_TAG 32'h00000001
......
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