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White Rabbit core collection
Commit 8f256824 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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gsi: projects now work with hdlmake

parent 378bc37d
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Showing with 323 additions and 464 deletions
platform/altera/Manifest.py
View file @ 8f256824
files = [ "altera_pkg.vhd", "flash_loader.vhd", "pow_reset.vhd" ] files = [ "altera_pkg.vhd", "flash_loader.vhd", "pow_reset.vhd" ]
modules = {"local":"wr_gxb_phy_arria2"} modules = {"local": [ "wr_gxb_phy_arria2", "dmtd_clk_pll", "sys_pll" ] }
\ No newline at end of file
platform/altera/dmtd_clk_pll/Manifest.py 0 → 100644
View file @ 8f256824
files = [ "dmtd_clk_pll.vhd" ]
platform/altera/sys_pll/Manifest.py 0 → 100644
View file @ 8f256824
files = [ "sys_pll.vhd" ]
syn/gsi_exploder/wr_core_demo/Manifest.py
View file @ 8f256824
...@@ -3,8 +3,8 @@ action = "synthesis" ...@@ -3,8 +3,8 @@ action = "synthesis"
fetchto = "../../../ip_cores" fetchto = "../../../ip_cores"
syn_device = "ep2agx125ef" syn_device = "ep2agx125df"
syn_grade = "c5" syn_grade = "c6"
syn_package = "25" syn_package = "25"
syn_top = "exploder_top" syn_top = "exploder_top"
syn_project = "exploder_top" syn_project = "exploder_top"
......
syn/gsi_exploder/wr_core_demo/exploder_top.qpf
View file @ 8f256824
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 11.1 Build 173 11/01/2011 SJ Full Version
# Date created = 11:45:41 February 14, 2012
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "11.1"
DATE = "11:45:41 February 14, 2012"
# Revisions
PROJECT_REVISION = "exploder_top" PROJECT_REVISION = "exploder_top"
syn/gsi_scu/wr_core_demo/Manifest.py
View file @ 8f256824
...@@ -10,5 +10,3 @@ syn_top = "scu_top" ...@@ -10,5 +10,3 @@ syn_top = "scu_top"
syn_project = "scu" syn_project = "scu"
modules = {"local" : [ "../../../", "../../../top/gsi_scu/wr_core_demo"]} modules = {"local" : [ "../../../", "../../../top/gsi_scu/wr_core_demo"]}
syn/gsi_scu/wr_core_demo/scu.qpf
View file @ 8f256824
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 11.1 Build 173 11/01/2011 SJ Full Version
# Date created = 11:00:37 February 13, 2012
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "11.1"
DATE = "11:00:37 February 13, 2012"
# Revisions
PROJECT_REVISION = "scu" PROJECT_REVISION = "scu"
PROJECT_REVISION = "exploder_ng"
syn/gsi_scu/wr_core_demo/scu.qsf
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This diff is collapsed.
top/gsi_exploder/wr_core_demo/Manifest.py
View file @ 8f256824
fetchto = "../../../ip_cores" fetchto = "../../../ip_cores"
modules = { modules = {
"local" : "../../../modules/mini_bone",
"git" : "git://ohwr.org/hdl-core-lib/etherbone-core.git" "git" : "git://ohwr.org/hdl-core-lib/etherbone-core.git"
}; };
files = ["exploder_top.sdc", "exploder_top.vhd", "pow_reset.vhd", "spec_serial_dac.vhd", "flash_loader.vhd"] files = ["exploder_top.sdc", "exploder_top.vhd" ]
top/gsi_scu/wr_core_demo/Manifest.py
View file @ 8f256824
fetchto = "../../../ip_cores" fetchto = "../../../ip_cores"
modules = { modules = {
"local" : "../../../modules/mini_bone",
"git" : "git://ohwr.org/hdl-core-lib/etherbone-core.git" "git" : "git://ohwr.org/hdl-core-lib/etherbone-core.git"
}; };
files = ["scu_top.vhd"] files = ["scu_top.vhd", "scu_top.sdc"]
top/gsi_scu/wr_core_demo/scu_top.vhd
View file @ 8f256824
...@@ -12,7 +12,6 @@ use work.eca_pkg.all; ...@@ -12,7 +12,6 @@ use work.eca_pkg.all;
use work.wb_cores_pkg_gsi.all; use work.wb_cores_pkg_gsi.all;
use work.pcie_wb_pkg.all; use work.pcie_wb_pkg.all;
use work.wr_altera_pkg.all; use work.wr_altera_pkg.all;
use work.lpc_uart_pkg.all;
use work.etherbone_pkg.all; use work.etherbone_pkg.all;
entity scu_top is entity scu_top is
......
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