wr_gtp_phy: generate 2-cycle long RXSLIDE pulses for Ultrascale(+) family

8a4c3198 · Tomasz Wlostowski · Grzegorz Daniluk · 76bd85c4 · 8a4c3198
Commit 8a4c3198 authored Jul 28, 2020 by Tomasz Wlostowski Committed by Grzegorz Daniluk Sep 15, 2020
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gtp_bitslide.vhd platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd +10 -2

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--- a/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
+++ b/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2010-11-18
-- Last update: 2013-12-20
+-- Last update: 2020-07-03
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -201,7 +201,15 @@ begin  -- behavioral
        when S_PAUSE =>
          counter        <= counter + 1;
-          gtp_rx_slide_o <= '0';
+          if g_target = "ultrascale" then
+            if counter = 1 then
+              gtp_rx_slide_o <= '0'; -- ultrascale requires 2 RXUSRCLK2 ticks
+                                     -- for slide pulse
+            end if;
+          else
+            gtp_rx_slide_o <= '0';
+          end if;
          if(counter = to_unsigned(c_pause_tics, counter'length)) then