Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
8969dbb0
Commit
8969dbb0
authored
Oct 26, 2011
by
Grzegorz Daniluk
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
pps_gen: adding xwb module
parent
bd46dc5b
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
122 additions
and
1 deletion
+122
-1
Manifest.py
modules/wrsw_pps_gen/Manifest.py
+2
-1
xwb_pps_gen.vhd
modules/wrsw_pps_gen/xwb_pps_gen.vhd
+120
-0
No files found.
modules/wrsw_pps_gen/Manifest.py
View file @
8969dbb0
files
=
[
"pps_gen_wb.vhd"
,
"wrsw_pps_gen.vhd"
];
\ No newline at end of file
"wrsw_pps_gen.vhd"
,
"xwb_pps_gen.vhd"
];
modules/wrsw_pps_gen/xwb_pps_gen.vhd
0 → 100644
View file @
8969dbb0
-------------------------------------------------------------------------------
-- Title : PPS Generator & UTC Realtime clock
-- Project : WhiteRabbit Switch
-------------------------------------------------------------------------------
-- File : xwb_pps_gen.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-09-02
-- Last update: 2011-10-26
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-09-02 1.0 twlostow Created
-- 2011-05-09 1.1 twlostow Added external PPS input
-- 2011-10-26 1.2 greg.d xwb module
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
xwb_pps_gen
is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
port
(
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_o
:
out
t_wishbone_slave_out
;
pps_in_i
:
in
std_logic
;
-- Single-pulse PPS output for synchronizing endpoints to
pps_csync_o
:
out
std_logic
;
pps_out_o
:
out
std_logic
;
pps_val_o
:
out
std_logic
;
tc_utc_o
:
out
std_logic_vector
(
39
downto
0
);
tc_nsec_o
:
out
std_logic_vector
(
27
downto
0
);
tc_val_o
:
out
std_logic
);
end
xwb_pps_gen
;
architecture
behavioral
of
xwb_pps_gen
is
component
wrsw_pps_gen
is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
;
g_address_granularity
:
t_wishbone_address_granularity
);
port
(
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
wb_addr_i
:
in
std_logic_vector
(
3
downto
0
);
wb_data_i
:
in
std_logic_vector
(
31
downto
0
);
wb_data_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
pps_in_i
:
in
std_logic
;
pps_csync_o
:
out
std_logic
;
pps_out_o
:
out
std_logic
;
pps_val_o
:
out
std_logic
;
tc_utc_o
:
out
std_logic_vector
(
39
downto
0
);
tc_nsec_o
:
out
std_logic_vector
(
27
downto
0
);
tc_val_o
:
out
std_logic
);
end
component
;
begin
-- behavioral
WRAPPED_PPSGEN
:
wrsw_pps_gen
generic
map
(
g_interface_mode
=>
g_interface_mode
,
g_address_granularity
=>
g_address_granularity
)
port
map
(
clk_ref_i
=>
clk_ref_i
,
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
wb_addr_i
=>
slave_i
.
adr
(
3
downto
0
),
wb_data_i
=>
slave_i
.
dat
,
wb_data_o
=>
slave_o
.
dat
,
wb_cyc_i
=>
slave_i
.
cyc
,
wb_sel_i
=>
slave_i
.
sel
,
wb_stb_i
=>
slave_i
.
stb
,
wb_we_i
=>
slave_i
.
we
,
wb_ack_o
=>
slave_o
.
ack
,
wb_stall_o
=>
slave_o
.
stall
,
pps_in_i
=>
pps_in_i
,
pps_csync_o
=>
pps_csync_o
,
pps_out_o
=>
pps_out_o
,
pps_val_o
=>
pps_val_o
,
tc_utc_o
=>
tc_utc_o
,
tc_nsec_o
=>
tc_nsec_o
,
tc_val_o
=>
tc_val_o
);
end
behavioral
;
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment