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White Rabbit core collection
Commit 881d7258 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'use-genrams' 

Conflicts:
	modules/wr_tlu/wb_timestamp_latch.vhd
parents c10c2e90 f7682900
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modules/lpc_uart/Manifest.py deleted 100644 → 0
View file @ c10c2e90
files = [
"lpc_peripheral.vhd",
"lpc_uart.vhd",
"lpc_uart_pkg.vhd",
"postcode.vhd",
"serirq_defines.v",
"serirq_slave.v"
]
modules/lpc_uart/lpc_peripheral.vhd deleted 100644 → 0
View file @ c10c2e90
This diff is collapsed.
modules/lpc_uart/lpc_uart.vhd deleted 100644 → 0
View file @ c10c2e90
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity lpc_uart is
port (
lpc_clk: in std_logic;
lpc_serirq: inout std_logic;
lpc_ad: inout std_logic_vector(3 downto 0);
lpc_frame_n: in std_logic;
lpc_reset_n: in std_logic;
serial_rxd: in std_logic;
serial_txd: out std_logic;
serial_dtr: out std_logic;
serial_dcd: in std_logic;
serial_dsr: in std_logic;
serial_ri: in std_logic;
serial_cts: in std_logic;
serial_rts: out std_logic;
seven_seg_L: out std_logic_vector(7 downto 0); -- SSeg Data output
seven_seg_H: out std_logic_vector(7 downto 0) -- SSeg Data output
);
end lpc_uart;
architecture lpc_uart_arch of lpc_uart is
component lpc_decoder is
Port (
lclk: in std_logic; -- LPC: 33MHz clock (rising edge)
lframe_n: in std_logic; -- LPC: frame, active low
lreset_n: in std_logic; -- LPC: reset, active low
lad: in std_logic_vector(3 downto 0); -- LPC: multiplexed bus
paddr: out std_logic_vector(15 downto 0); -- port addr
pdata_in: out std_logic_vector(7 downto 0); -- data to the slave
pdata_out: in std_logic_vector(7 downto 0); -- data from the slave
paddr_valid: out std_logic;
pdata_valid: out std_logic
);
end component;
component lpc_peripheral is
port (
clk_i: in std_logic;
nrst_i: in std_logic;
lframe_i: in std_logic; -- LPC Frame input (active high)
lad_oe: out std_logic; -- LPC AD Output Enable
lad_i: in std_logic_vector(3 downto 0); -- LPC AD Input Bus
lad_o: out std_logic_vector(3 downto 0); -- LPC AD Output Bus
dma_chan_o: out std_logic_vector(2 downto 0); -- DMA Channel
dma_tc_o: out std_logic; -- DMA Terminal Count
wbm_err_i: in std_logic;
io_bus_dat_o: out std_logic_vector(7 downto 0);
io_bus_dat_i: in std_logic_vector(7 downto 0);
io_bus_addr: out std_logic_vector(15 downto 0);
io_bus_we: out std_logic;
io_ack: in std_logic;
io_data_valid: out std_logic
);
end component;
component postcode is
port (
lclk: in std_logic;
paddr: in std_logic_vector(15 downto 0);
pdata: in std_logic_vector(7 downto 0);
addr_hit: out std_logic;
data_valid: in std_logic;
seven_seg_L: out std_logic_vector(7 downto 0); -- SSeg Data output
seven_seg_H: out std_logic_vector(7 downto 0) -- SSeg Data output
);
end component;
component uart_16750 is
port (
CLK : in std_logic; -- Clock 24Mhz
RST : in std_logic; -- Reset
BAUDCE : in std_logic; -- Baudrate generator clock enable
CS : in std_logic; -- Chip select
WR : in std_logic; -- Write to UART
RD : in std_logic; -- Read from UART
A : in std_logic_vector(2 downto 0); -- Register select
DIN : in std_logic_vector(7 downto 0); -- Data bus input
DOUT : out std_logic_vector(7 downto 0); -- Data bus output
DDIS : out std_logic; -- Driver disable
INT : out std_logic; -- Interrupt output
OUT1N : out std_logic; -- Output 1
OUT2N : out std_logic; -- Output 2
RCLK : in std_logic; -- Receiver clock (16x baudrate)
BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
RTSN : out std_logic; -- RTS output
DTRN : out std_logic; -- DTR output
CTSN : in std_logic; -- CTS input
DSRN : in std_logic; -- DSR input
DCDN : in std_logic; -- DCD input
RIN : in std_logic; -- RI input
SIN : in std_logic; -- Receiver input
SOUT : out std_logic -- Transmitter output
);
end component;
component uart_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC;
c1 : out std_logic
);
END component;
component serirq_slave is
port (
clk_i : in std_logic;
nrst_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0);
serirq_o : out std_logic;
serirq_i : in std_logic;
serirq_oe : out std_logic
);
end component;
constant uart_base_addr: unsigned(15 downto 0) := x"03F8";
signal io_addr: std_logic_vector(15 downto 0);
signal io_to_slave: std_logic_vector(7 downto 0);
signal io_from_slave: std_logic_vector(7 downto 0);
signal s_paddr_valid: std_logic;
signal s_pdata_valid: std_logic;
signal clk_24: std_logic;
signal s_baudout: std_logic;
signal s_uart_addr: std_logic_vector(2 downto 0);
signal s_uart_cs: std_logic;
signal s_addr_hit: std_logic;
signal s_rd_en: std_logic;
signal s_wr_en: std_logic;
signal io_bus_we: std_logic;
signal s_lad_i: std_logic_vector(3 downto 0);
signal s_lad_o: std_logic_vector(3 downto 0);
signal lad_oe: std_logic;
signal io_data_valid: std_logic;
signal rst: std_logic;
signal serirq_i: std_logic;
signal serirq_o: std_logic;
signal serirq_oe: std_logic;
signal irq_vector: std_logic_vector(31 downto 0);
signal uart_int: std_logic;
begin
rst <= not lpc_reset_n;
s_wr_en <= io_bus_we and io_data_valid;
s_rd_en <= not io_bus_we and io_data_valid;
irq_vector <= x"FFFFFF" & "111" & not uart_int & "1111"; -- IRQ4 is IRQ frame 4 on CA945
decoder: lpc_peripheral port map (
clk_i => lpc_clk,
lframe_i => lpc_frame_n,
nrst_i => lpc_reset_n,
lad_oe => lad_oe,
lad_i => s_lad_i,
lad_o => s_lad_o,
dma_chan_o => open,
dma_tc_o => open,
wbm_err_i => '0',
io_bus_dat_o => io_to_slave,
io_bus_dat_i => io_from_slave,
io_bus_addr => io_addr,
io_bus_we => io_bus_we,
io_ack => '1',
io_data_valid => io_data_valid
);
pcode: postcode port map (
lclk => lpc_clk,
data_valid => io_data_valid,
paddr => io_addr,
pdata => io_to_slave,
addr_hit => s_addr_hit,
seven_seg_L => seven_seg_L,
seven_seg_H => seven_seg_H
);
uart: uart_16750 port map (
clk => lpc_clk,
rst => rst,
baudce => '1',
cs => s_uart_cs,
wr => s_wr_en,
rd => s_rd_en,
a => s_uart_addr,
din => io_to_slave,
dout => io_from_slave,
ddis => open,
int => uart_int,
out1n => open,
out2n => open,
rclk => s_baudout,
baudoutn => s_baudout,
rtsn => serial_rts,
dtrn => serial_dtr,
ctsn => serial_cts,
dsrn => serial_dsr,
dcdn => serial_dcd,
rin => serial_ri,
sin => serial_rxd,
sout => serial_txd
);
serirq: serirq_slave port map (
clk_i => lpc_clk,
nrst_i => lpc_reset_n,
irq_i => irq_vector,
serirq_o => serirq_o,
serirq_i => serirq_i,
serirq_oe => serirq_oe
);
tri_lad: process (lad_oe)
begin
if lad_oe = '1' then
lpc_ad <= s_lad_o;
else
lpc_ad <= (others => 'Z');
end if;
end process;
s_lad_i <= lpc_ad;
tri_serirq: process (serirq_oe)
begin
if serirq_oe = '1' then
lpc_serirq <= serirq_o;
else
lpc_serirq <= 'Z';
end if;
end process;
serirq_i <= lpc_serirq;
uart_addr_deco: process (lpc_clk, io_addr)
begin
if rising_edge(lpc_clk) then
case unsigned(io_addr) is
when (uart_base_addr + 0) => s_uart_addr <= "000";
s_uart_cs <= '1';
when (uart_base_addr + 1) => s_uart_addr <= "001";
s_uart_cs <= '1';
when (uart_base_addr + 2) => s_uart_addr <= "010";
s_uart_cs <= '1';
when (uart_base_addr + 3) => s_uart_addr <= "011";
s_uart_cs <= '1';
when (uart_base_addr + 4) => s_uart_addr <= "100";
s_uart_cs <= '1';
when (uart_base_addr + 5) => s_uart_addr <= "101";
s_uart_cs <= '1';
when (uart_base_addr + 6) => s_uart_addr <= "110";
s_uart_cs <= '1';
when (uart_base_addr + 7) => s_uart_addr <= "111";
s_uart_cs <= '1';
when others => s_uart_addr <= "000";
s_uart_cs <= '0';
end case;
end if;
end process;
end architecture;
\ No newline at end of file
modules/lpc_uart/lpc_uart_pkg.vhd deleted 100644 → 0
View file @ c10c2e90
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
package lpc_uart_pkg is
component lpc_uart is
port (
lpc_clk: in std_logic;
lpc_serirq: inout std_logic;
lpc_ad: inout std_logic_vector(3 downto 0);
lpc_frame_n: in std_logic;
lpc_reset_n: in std_logic;
serial_rxd: in std_logic;
serial_txd: out std_logic;
serial_dtr: out std_logic;
serial_dcd: in std_logic;
serial_dsr: in std_logic;
serial_ri: in std_logic;
serial_cts: in std_logic;
serial_rts: out std_logic;
seven_seg_L: out std_logic_vector(7 downto 0); -- SSeg Data output
seven_seg_H: out std_logic_vector(7 downto 0) -- SSeg Data output
);
end component;
end lpc_uart_pkg;
modules/lpc_uart/postcode.vhd deleted 100644 → 0
View file @ c10c2e90
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity postcode is
port (
lclk: in std_logic;
pdata_valid: in std_logic;
paddr_valid: in std_logic;
paddr: in std_logic_vector(15 downto 0);
pdata: in std_logic_vector(7 downto 0);
addr_hit: out std_logic;
data_valid: in std_logic;
seven_seg_L: out std_logic_vector(7 downto 0); -- SSeg Data output
seven_seg_H: out std_logic_vector(7 downto 0) -- SSeg Data output
);
end entity;
architecture postcode_arch of postcode is
signal postcode_data: std_logic_vector(7 downto 0);
constant postcode_addr: std_logic_vector(15 downto 0) := x"0080";
begin
postcode_reg: process(lclk)
begin
if rising_edge(lclk) then
if (paddr = postcode_addr and data_valid = '1') then
addr_hit <= '1';
postcode_data <= pdata;
else
addr_hit <= '0';
end if;
end if;
end process;
P_sseg_decode: process(lclk) -- decode section for 7 seg displays
begin
if rising_edge(lclk) then
case postcode_data(7 downto 4) is -- Most sig digit for display
when "0000" => seven_seg_H <= "00000011"; -- Hex 03 displays a 0
when "0001" => seven_seg_H <= "10011111"; -- Hex 9f displays a 1
when "0010" => seven_seg_H <= "00100101"; -- Hex 25 displays a 2
when "0011" => seven_seg_H <= "00001101"; -- Hex 0d displays a 3
when "0100" => seven_seg_H <= "10011001"; -- Hex 99 displays a 4
when "0101" => seven_seg_H <= "01001001"; -- Hex 49 displays a 5
when "0110" => seven_seg_H <= "01000001"; -- Hex 41 displays a 6
when "0111" => seven_seg_H <= "00011111"; -- Hex 1f displays a 7
when "1000" => seven_seg_H <= "00000001"; -- Hex 01 displays a 8
when "1001" => seven_seg_H <= "00001001"; -- Hex 09 displays a 9
when "1010" => seven_seg_H <= "00010001"; -- Hex 11 displays a A
when "1011" => seven_seg_H <= "11000001"; -- Hex c1 displays a b
when "1100" => seven_seg_H <= "01100011"; -- Hex 63 displays a C
when "1101" => seven_seg_H <= "10000101"; -- Hex 85 displays a d
when "1110" => seven_seg_H <= "01100001"; -- Hex 61 displays a E
when "1111" => seven_seg_H <= "01110001"; -- Hex 71 displays a F
when others => seven_seg_H <= "00000001"; -- Hex 01 displays a 8
end case;
case postcode_data(3 downto 0) is -- Least sig digit for display
when "0000" => seven_seg_L <= "00000011"; -- Hex 03 displays a 0
when "0001" => seven_seg_L <= "10011111"; -- Hex 9f displays a 1
when "0010" => seven_seg_L <= "00100101"; -- Hex 25 displays a 2
when "0011" => seven_seg_L <= "00001101"; -- Hex 0d displays a 3
when "0100" => seven_seg_L <= "10011001"; -- Hex 99 displays a 4
when "0101" => seven_seg_L <= "01001001"; -- Hex 49 displays a 5
when "0110" => seven_seg_L <= "01000001"; -- Hex 41 displays a 6
when "0111" => seven_seg_L <= "00011111"; -- Hex 1f displays a 7
when "1000" => seven_seg_L <= "00000001"; -- Hex 01 displays a 8
when "1001" => seven_seg_L <= "00001001"; -- Hex 09 displays a 9
when "1010" => seven_seg_L <= "00010001"; -- Hex 11 displays a A
when "1011" => seven_seg_L <= "11000001"; -- Hex c1 displays a b
when "1100" => seven_seg_L <= "01100011"; -- Hex 63 displays a C
when "1101" => seven_seg_L <= "10000101"; -- Hex 85 displays a d
when "1110" => seven_seg_L <= "01100001"; -- Hex 61 displays a E
when "1111" => seven_seg_L <= "01110001"; -- Hex 71 displays a F
when others => seven_seg_L <= "00000001"; -- Hex 01 displays a 8
end case;
end if;
end process;
end architecture;
\ No newline at end of file
modules/lpc_uart/serirq_defines.v deleted 100644 → 0
View file @ c10c2e90
//////////////////////////////////////////////////////////////////////
//// ////
//// $Id: serirq_defines.v,v 1.2 2008-12-27 19:46:18 hharte Exp $
//// wb_lpc_defines.v ////
//// ////
//// This file is part of the Wishbone LPC Bridge project ////
//// http://www.opencores.org/projects/wb_lpc/ ////
//// ////
//// Author: ////
//// - Howard M. Harte (hharte@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Howard M. Harte ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Wishbone SERIRQ Host/Slave Interface Definitions
`define SERIRQ_ST_IDLE 13'h000 // SERIRQ Idle state
`define SERIRQ_ST_START 13'h001 // SERIRQ Start state
`define SERIRQ_ST_START_R 13'h002 // SERIRQ Start state
`define SERIRQ_ST_START_T 13'h004 // SERIRQ Start state
`define SERIRQ_ST_IRQ 13'h008 // SERIRQ IRQ Frame State
`define SERIRQ_ST_IRQ_R 13'h010 // SERIRQ IRQ Frame State
`define SERIRQ_ST_IRQ_T 13'h020 // SERIRQ IRQ Frame State
`define SERIRQ_ST_STOP 13'h040 // SERIRQ Stop State
`define SERIRQ_ST_STOP_R 13'h080 // SERIRQ Stop State
`define SERIRQ_ST_STOP_T 13'h100 // SERIRQ Stop State
`define SERIRQ_ST_WAIT_STOP 13'h200
`define SERIRQ_MODE_CONTINUOUS 1'b1 // Serirq "Continuous Mode"
`define SERIRQ_MODE_QUIET 1'b0 // Serirq "Quiet Mode"
\ No newline at end of file
modules/lpc_uart/serirq_slave.v deleted 100644 → 0
View file @ c10c2e90
//////////////////////////////////////////////////////////////////////
//// ////
//// $Id: serirq_slave.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////
//// serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge ////
//// ////
//// This file is part of the Wishbone LPC Bridge project ////
//// http://www.opencores.org/projects/lpc/ ////
//// ////
//// Author: ////
//// - Howard M. Harte (hharte@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Howard M. Harte ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ns
`include "serirq_defines.v"
module serirq_slave(clk_i, nrst_i,
irq_i,
serirq_o, serirq_i, serirq_oe
);
// Wishbone Slave Interface
input clk_i;
input nrst_i; // Active low reset.
// SERIRQ Master Interface
output reg serirq_o; // SERIRQ output
input serirq_i; // SERIRQ Input
output reg serirq_oe; // SERIRQ Output Enable
input [31:0] irq_i; // IRQ Input Bus
reg [31:0] current_irq;
reg [12:0] state; // Current state
reg [4:0] irq_cnt; // IRQ Frame counter
reg found_stop;
reg found_start;
reg serirq_mode;
wire irq_changed = (serirq_mode & (current_irq != irq_i));
always @(posedge clk_i or negedge nrst_i)
if(~nrst_i)
begin
state <= `SERIRQ_ST_IDLE;
serirq_oe <= 1'b0;
serirq_o <= 4'b1;
irq_cnt <= 5'h00;
current_irq <= irq_i;
end
else begin
case(state)
`SERIRQ_ST_IDLE:
begin
serirq_oe <= 1'b0;
irq_cnt <= 5'h00;
serirq_o <= 1'b1;
if(found_start == 1'b1) // Wait for Start cycle
begin
current_irq <= irq_i;
if(irq_i[irq_cnt] == 1'b0) begin
serirq_oe <= 1'b1;
serirq_o <= 1'b0;
end
state <= `SERIRQ_ST_IRQ_R;
end
else if(irq_changed) begin
current_irq <= irq_i;
serirq_o <= 1'b0;
serirq_oe <= 1'b1;
state <= `SERIRQ_ST_IDLE;
end else
state <= `SERIRQ_ST_IDLE;
end
`SERIRQ_ST_IRQ:
begin
if(irq_i[irq_cnt] == 1'b0) begin
serirq_oe <= 1'b1;
serirq_o <= 1'b0;
end
if(found_stop == 1'b0)
state <= `SERIRQ_ST_IRQ_R;
else
state <= `SERIRQ_ST_IDLE;
end
`SERIRQ_ST_IRQ_R:
begin
serirq_o <= 1'b1;
if(found_stop == 1'b0)
state <= `SERIRQ_ST_IRQ_T;
else
state <= `SERIRQ_ST_IDLE;
end
`SERIRQ_ST_IRQ_T:
begin
serirq_oe <= 1'b0;
if(irq_cnt == 5'h1f)
begin
state <= `SERIRQ_ST_WAIT_STOP;
end
else begin
irq_cnt <= irq_cnt + 1;
if(found_stop == 1'b0)
state <= `SERIRQ_ST_IRQ;
else
state <= `SERIRQ_ST_IDLE;
end
end
`SERIRQ_ST_WAIT_STOP:
begin
if(found_stop == 1'b0)
state <= `SERIRQ_ST_WAIT_STOP;
else
state <= `SERIRQ_ST_IDLE;
end
endcase
end
reg [3:0] stop_clk_cnt;
// Look for STOP cycles
always @(posedge clk_i or negedge nrst_i)
if(~nrst_i)
begin
found_stop <= 1'b0;
found_start <= 1'b0;
serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
stop_clk_cnt <= 4'h0;
end
else begin
if(serirq_i == 1'b0) begin
stop_clk_cnt <= stop_clk_cnt + 1;
end
else begin
case (stop_clk_cnt)
4'h2:
begin
found_stop <= 1'b1;
found_start <= 1'b0;
serirq_mode <= `SERIRQ_MODE_QUIET;
end
4'h3:
begin
found_stop <= 1'b1;
found_start <= 1'b0;
serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
end
4'h4:
begin
found_stop <= 1'b0;
found_start <= 1'b1;
end
4'h6:
begin
found_stop <= 1'b0;
found_start <= 1'b1;
end
4'h8:
begin
found_stop <= 1'b0;
found_start <= 1'b1;
end
default:
begin
found_stop <= 1'b0;
found_start <= 1'b0;
end
endcase
stop_clk_cnt <= 4'h0;
end
end
endmodule
\ No newline at end of file
modules/wr_eca/eca-ctl.cpp
View file @ 881d7258
......@@ -251,7 +251,10 @@ int main(int argc, char** argv) {
if ((status = socket.open()) != EB_OK) die(status, "etherbone::socket.open");
Device device;
if ((status = device.open(socket, devpath)) != EB_OK) die(status, "etherbone::device.open");
if ((status = device.open(socket, devpath)) != EB_OK) {
fprintf(stderr, "%s: etherbone::device.open('%s') -- %s\n", program, devpath, eb_status(status));
return 1;
}
std::vector<ECA> ecas;
if ((status = ECA::load(device, ecas)) != EB_OK) die(status, "ECA::load");
......
modules/wr_eca/eca-table.cpp
View file @ 881d7258
......@@ -214,7 +214,10 @@ int main(int argc, char** argv) {
if ((status = socket.open()) != EB_OK) die(status, "etherbone::socket.open");
Device device;
if ((status = device.open(socket, devpath)) != EB_OK) die(status, "etherbone::device.open");
if ((status = device.open(socket, devpath)) != EB_OK) {
fprintf(stderr, "%s: etherbone::device.open('%s') -- %s\n", program, devpath, eb_status(status));
return 1;
}
std::vector<ECA> ecas;
if ((status = ECA::load(device, ecas)) != EB_OK) die(status, "ECA::load");
......
modules/wr_eca/eca_channel.vhd
View file @ 881d7258
......@@ -195,7 +195,7 @@ architecture rtl of eca_channel is
signal dispatch_mux_record : t_mux_record;
-- Scan registers
signal scan_time : t_time_array (c_scanners-1 downto 0);
signal scan_time_n : t_time_array (c_scanners-1 downto 0);
signal scan_time_idx : t_queue_index_array(c_scanners-1 downto 0);
signal scan_index : t_table_lo_index_array(3 downto 1) := (others => (others => '0'));
......@@ -203,6 +203,7 @@ architecture rtl of eca_channel is
signal scan_next : t_table_lo_index;
signal scan_time_p4 : t_queue_index;
signal scan_time_m4 : t_queue_index;
signal scan_valid3 : std_logic_vector(c_scanners-1 downto 0);
signal scan_valid2 : std_logic_vector(c_scanners-1 downto 0);
signal scan_valid1 : std_logic_vector(c_scanners-1 downto 0);
signal scan_lesseq : std_logic_vector(c_scanners-1 downto 0);
......@@ -264,8 +265,9 @@ begin
TSx : for table_hi_idx in 0 to c_scanners-1 generate
TS : eca_sdp
generic map(
g_addr_bits => c_table_lo_index_bits,
g_data_bits => c_time_bits+1)
g_addr_bits => c_table_lo_index_bits,
g_data_bits => c_time_bits+1,
g_dual_clock => false)
port map(
w_clk_i => clk_i,
w_en_i => ts_manage_write(table_hi_idx),
......@@ -281,8 +283,9 @@ begin
-- The data part of the table
TD : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => cd_data_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => cd_data_bits,
g_dual_clock => false)
port map(
w_clk_i => clk_i,
w_en_i => td_manage_write,
......@@ -303,8 +306,9 @@ begin
-- The free queue
F : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_index_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_index_bits,
g_dual_clock => false)
port map(
w_clk_i => clk_i,
w_en_i => fw_manage_free,
......@@ -411,11 +415,15 @@ begin
begin
if rising_edge(clk_i) then
-- No reset; logic is acyclic
scan_valid2(table_hi_idx) <= ts_scan_valid(table_hi_idx);
scan_time (table_hi_idx) <= ts_scan_time(table_hi_idx);
scan_valid3(table_hi_idx) <= -- beware of RW conflict on memory
f_eca_active_high(ts_manage_index(table_hi_idx) /= ts_scan_index(table_hi_idx));
scan_valid2(table_hi_idx) <= ts_scan_valid(table_hi_idx) and scan_valid3(table_hi_idx);
scan_time_n(table_hi_idx) <= not ts_scan_time(table_hi_idx);
scan_valid1(table_hi_idx) <= scan_valid2(table_hi_idx);
time_idx := scan_time(table_hi_idx)(time_idx'range);
time_idx := not scan_time_n(table_hi_idx)(time_idx'range);
scan_time_idx(table_hi_idx) <= time_idx;
-- pipeline hazard if: (time_idx - (time_i - 4)) <= 12
scan_hazard(table_hi_idx) <=
......@@ -432,7 +440,7 @@ begin
port map(
clk_i => clk_i,
a_i => time_Q_i,
b_i => not scan_time(table_hi_idx),
b_i => scan_time_n(table_hi_idx),
c_i => '1',
c1_o => scan_lesseq(table_hi_idx),
x2_o => open,
......
modules/wr_eca/eca_gpio_channel.vhd
View file @ 881d7258
......@@ -5,8 +5,8 @@
--! Copyright (C) 2013 GSI Helmholtz Centre for Heavy Ion Research GmbH
--!
--! This component takes an action channel and turns it into a GPIO controller.
--! The tag determines the action taken on the outputs; the state of the IO is:
--! io(x) <= (tag(16+x) and io(x)) xor tag(x);
--! The 32-bit tag is interpretted as (16-bit clear, 16-bit set).
--! When both clear and set appear, the output is instead toggled.
--!
--------------------------------------------------------------------------------
--! This library is free software; you can redistribute it and/or
......@@ -49,13 +49,19 @@ begin
gpio_o <= r_gpio;
main : process(clk_i) is
variable v_set : std_logic_vector(15 downto 0);
variable v_clr : std_logic_vector(15 downto 0);
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
r_gpio <= (others => '0');
else
if channel_i.valid = '1' then
r_gpio <= (r_gpio and channel_i.tag(31 downto 16)) xor channel_i.tag(15 downto 0);
v_set := channel_i.tag(15 downto 0);
v_clr := channel_i.tag(31 downto 16);
r_gpio <= ((not v_set) and (not v_clr) and ( r_gpio)) or -- unmodified
(( v_set) and ( v_clr) and (not r_gpio)) or -- toggled
(( v_set) and (not v_clr)); -- set
end if;
end if;
end if;
......
modules/wr_eca/eca_pkg.vhd
View file @ 881d7258
......@@ -184,12 +184,12 @@ package eca_pkg is
function f_eca_gray_decode(x : std_logic_vector; step : natural) return std_logic_vector;
-- Registers its inputs. Async outputs.
-- When r_clk_i=w_clk_i and r_addr_i=w_addr_i, r_data_o return old data (not w_data_i).
-- If r_clk_i /= w_clk_i, then r_data_o is undefined.
-- When r_addr_i=w_addr_i, r_data_o is undefined.
component eca_sdp is
generic(
g_addr_bits : natural := 8;
g_data_bits : natural := 8);
g_addr_bits : natural := 8;
g_data_bits : natural := 8;
g_dual_clock : boolean);
port(
r_clk_i : in std_logic;
r_addr_i : in std_logic_vector(g_addr_bits-1 downto 0);
......
modules/wr_eca/eca_sdp.vhd
View file @ 881d7258
......@@ -27,16 +27,19 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.eca_pkg.all;
use work.genram_pkg.all;
-- Registers its inputs. Async outputs.
-- When r_clk_i=w_clk_i and r_addr_i=w_addr_i, r_data_o return old data (not w_data_i).
-- If r_clk_i /= w_clk_i, then r_data_o is undefined.
entity eca_sdp is
generic(
g_addr_bits : natural := 8;
g_data_bits : natural := 8);
g_addr_bits : natural := 8;
g_data_bits : natural := 8;
g_dual_clock : boolean);
port(
r_clk_i : in std_logic;
r_addr_i : in std_logic_vector(g_addr_bits-1 downto 0);
......@@ -48,27 +51,22 @@ entity eca_sdp is
end eca_sdp;
architecture rtl of eca_sdp is
type ram_t is array(2**g_addr_bits-1 downto 0) of
std_logic_vector(g_data_bits-1 downto 0);
signal ram : ram_t;
begin
r : process(r_clk_i)
begin
if rising_edge(r_clk_i) then
r_data_o <= ram(to_integer(unsigned(r_addr_i)));
end if;
end process;
w : process(w_clk_i)
begin
if rising_edge(w_clk_i) then
if w_en_i = '1' then
ram(to_integer(unsigned(w_addr_i))) <= w_data_i;
end if;
end if;
end process;
ram : generic_simple_dpram
generic map(
g_data_width => g_data_bits,
g_size => 2**g_addr_bits,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_dual_clock => g_dual_clock)
port map(
clka_i => w_clk_i,
wea_i => w_en_i,
aa_i => w_addr_i,
da_i => w_data_i,
clkb_i => r_clk_i,
ab_i => r_addr_i,
qb_o => r_data_o);
end rtl;
modules/wr_eca/eca_search.vhd
View file @ 881d7258
......@@ -151,8 +151,9 @@ begin
Active : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => c_data_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => c_data_bits,
g_dual_clock => true)
port map(
r_clk_i => clk_i,
r_addr_i(s3_probe'length) => r3_page,
......@@ -170,8 +171,9 @@ begin
Program : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => c_data_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => c_data_bits,
g_dual_clock => false)
port map(
r_clk_i => t_clk_i,
r_addr_i(t_addr_i'length) => t_page_i,
......
modules/wr_eca/eca_tdp.vhd
View file @ 881d7258
......@@ -58,7 +58,7 @@ architecture rtl of eca_tdp is
type ram_t is array(2**g_addr_bits-1 downto 0) of
std_logic_vector(g_data_bits-1 downto 0);
signal ram : ram_t;
signal ram : ram_t := (others => (others => '0'));
begin
a : process(a_clk_i)
......
modules/wr_eca/eca_walker.vhd
View file @ 881d7258
......@@ -143,8 +143,9 @@ begin
Active : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_data_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_data_bits,
g_dual_clock => true)
port map(
r_clk_i => clk_i,
r_addr_i(s_w_addr'length) => s_w_page,
......@@ -166,8 +167,9 @@ begin
Program : eca_sdp
generic map(
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_data_bits)
g_addr_bits => c_table_index_bits,
g_data_bits => c_table_data_bits,
g_dual_clock => false)
port map(
r_clk_i => t_clk_i,
r_addr_i(t_addr_i'length) => t_page_i,
......
modules/wr_eca/eca_wb_event.vhd
View file @ 881d7258
......@@ -108,8 +108,9 @@ begin
Q : eca_sdp
generic map(
g_addr_bits => c_addr1_bits,
g_data_bits => 32)
g_addr_bits => c_addr1_bits,
g_data_bits => 32,
g_dual_clock => true)
port map(
r_clk_i => e_clk_i,
r_addr_i => std_logic_vector(se_addr),
......
modules/wr_tlu/wb_timestamp_latch.vhd
View file @ 881d7258
......@@ -175,7 +175,6 @@ architecture behavioral of wb_timestamp_latch is
signal rd : channel;
signal we : channel;
signal rd_empty : channel;
signal rd_count : t_cnt_array;
signal wr_count : t_cnt_array;
......
modules/wrc_core/wr_core.vhd
View file @ 881d7258
......@@ -68,7 +68,6 @@ entity wr_core is
g_aux_clks : integer := 1;
g_rx_buffer_size : integer := 1024;
g_dpram_initf : string := "";
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_dpram_size : integer := 90112/4; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
......@@ -644,7 +643,6 @@ begin
generic map(
g_size => g_dpram_size,
g_init_file => g_dpram_initf,
g_init_value => g_dpram_initv,
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
......
modules/wrc_core/wrc_dpram.vhd
View file @ 881d7258
......@@ -69,7 +69,7 @@ begin
g_data_width => 32,
g_size => g_size,
g_with_byte_enable => true,
g_addr_conflict_resolution => "read_first",
g_addr_conflict_resolution => "dont_care",
g_init_file => g_init_file,
g_dual_clock => false
)
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 881d7258
......@@ -291,7 +291,6 @@ constant c_wrc_periph3_sdb : t_sdb_device := (
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_initf : string := "";
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_dpram_size : integer := 20480; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
......
modules/wrc_core/xwr_core.vhd
View file @ 881d7258
......@@ -54,7 +54,6 @@ entity xwr_core is
g_aux_clks : integer := 1;
g_ep_rxbuf_size : integer := 1024;
g_dpram_initf : string := "";
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_dpram_size : integer := 90112/4; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
......@@ -202,7 +201,6 @@ architecture struct of xwr_core is
g_aux_clks : integer := 1;
g_rx_buffer_size : integer := 12;
g_dpram_initf : string := "";
g_dpram_initv : t_xwb_dpram_init := c_xwb_dpram_init_nothing;
g_dpram_size : integer := 16384; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
......@@ -334,7 +332,6 @@ begin
g_with_external_clock_input => g_with_external_clock_input,
g_aux_clks => g_aux_clks,
g_dpram_initf => g_dpram_initf,
g_dpram_initv => g_dpram_initv,
g_dpram_size => g_dpram_size,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
......
platform/altera/altera_pkg.vhd
View file @ 881d7258
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
package wr_altera_pkg is
component flash_loader
......
platform/altera/sys_pll/sys_pll.vhd
View file @ 881d7258
......@@ -92,7 +92,6 @@ ARCHITECTURE SYN OF sys_pll IS
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
......@@ -192,12 +191,11 @@ BEGIN
clk4_duty_cycle => 50,
clk4_multiply_by => 4,
clk4_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 8000,
intended_device_family => "Arria II GX",
lpm_hint => "CBX_MODULE_PREFIX=sys_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
operation_mode => "NO_COMPENSATION",
pll_type => "Left_Right",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
......@@ -268,7 +266,7 @@ END SYN;
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
......@@ -319,7 +317,7 @@ END SYN;
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.50000000"
......@@ -406,11 +404,10 @@ END SYN;
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
......
platform/altera/wr_gxb_phy_arria2/arria_phy.vhd
View file @ 881d7258
......@@ -141,7 +141,7 @@
SIGNAL wire_tx_pll0_clk : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_tx_pll0_dprioout : STD_LOGIC_VECTOR (299 DOWNTO 0);
SIGNAL wire_tx_pll0_inclk : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_tx_pll0_locked : STD_LOGIC;
--SIGNAL wire_tx_pll0_locked : STD_LOGIC;
SIGNAL wire_receive_pcs0_bitslipboundaryselectout : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_receive_pcs0_cdrctrllocktorefcl : STD_LOGIC;
SIGNAL wire_w_lg_reconfig_togxb_busy307w : STD_LOGIC_VECTOR (0 DOWNTO 0);
......@@ -155,7 +155,7 @@
SIGNAL wire_receive_pcs0_pipepowerdown : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_receive_pcs0_pipepowerstate : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_receive_pcs0_rxfound : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_receive_pcs0_signaldetect : STD_LOGIC;
--SIGNAL wire_receive_pcs0_signaldetect : STD_LOGIC;
SIGNAL wire_receive_pcs0_xgmdatain : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_receive_pma0_analogtestbus : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_receive_pma0_clockout : STD_LOGIC;
......@@ -173,7 +173,7 @@
SIGNAL wire_transmit_pcs0_dispval : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_transmit_pcs0_dprioout : STD_LOGIC_VECTOR (149 DOWNTO 0);
SIGNAL wire_transmit_pcs0_forcedisp : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_transmit_pcs0_forceelecidleout : STD_LOGIC;
--SIGNAL wire_transmit_pcs0_forceelecidleout : STD_LOGIC;
SIGNAL wire_transmit_pcs0_powerdn : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_transmit_pcs0_revparallelfdbk : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL wire_transmit_pcs0_txdetectrx : STD_LOGIC;
......@@ -1697,7 +1697,7 @@
dprioin => pll0_dprioin(299 DOWNTO 0),
dprioout => wire_tx_pll0_dprioout,
inclk => wire_tx_pll0_inclk,
locked => wire_tx_pll0_locked,
locked => open, -- wire_tx_pll0_locked,
powerdown => pllpowerdn_in(0)
);
wire_receive_pcs0_cdrctrllocktorefcl <= wire_w_lg_reconfig_togxb_busy307w(0);
......@@ -1841,7 +1841,7 @@
rmfifowrena => wire_gnd,
rxdetectvalid => wire_gnd,
rxfound => wire_receive_pcs0_rxfound,
signaldetect => wire_receive_pcs0_signaldetect,
signaldetect => open, -- wire_receive_pcs0_signaldetect,
signaldetected => rx_signaldetect_wire(0),
xgmctrlin => wire_gnd,
xgmdatain => wire_receive_pcs0_xgmdatain
......@@ -1971,7 +1971,7 @@
enrevparallellpbk => wire_gnd,
forcedisp => wire_transmit_pcs0_forcedisp,
forcedispcompliance => wire_gnd,
forceelecidleout => wire_transmit_pcs0_forceelecidleout,
forceelecidleout => open, -- wire_transmit_pcs0_forceelecidleout,
invpol => tx_invpolarity(0),
localrefclk => tx_localrefclk(0),
phfiforddisable => wire_gnd,
......
platform/altera/wr_gxb_phy_arria2/wr_gxb_phy_arriaii.vhd
View file @ 881d7258
......@@ -138,7 +138,6 @@ architecture rtl of wr_gxb_phy_arriaii is
signal rx_seriallpbken : std_logic_vector (0 downto 0);
signal tx_clkout : std_logic_vector (0 downto 0);
signal tx_dataout : std_logic_vector (0 downto 0);
signal reconfig_busy : std_logic;
signal disp_pipe : std_logic_vector(1 downto 0);
signal cur_disp : t_8b10b_disparity;
......@@ -169,7 +168,7 @@ begin -- rtl
port map (
reconfig_clk => clk_reconf_i,
reconfig_fromgxb => reconfig_fromgxb,
busy => reconfig_busy,
busy => open,
reconfig_togxb => reconfig_togxb);
U_The_PHY : arria_phy
......
syn/gsi_exploder/wr_core_demo/Makefile 0 → 100644
View file @ 881d7258
TARGET = exploder_top
QUARTUS ?= /opt/quartus
QUARTUS_BIN = $(QUARTUS)/bin
all: $(TARGET).jam
clean:
rm -rf db incremental_db PLLJ_PLLSPE_INFO.txt
rm -f $(TARGET).*.rpt $(TARGET).*.summary $(TARGET).map* $(TARGET).fit.* $(TARGET).pin $(TARGET).jdi $(TARGET)*.qdf
rm -f $(TARGET).jam $(TARGET).jic $(TARGET).pof $(TARGET).sof $(TARGET).dep
%.sof: %.qsf
hdlmake
$(QUARTUS_BIN)/quartus_map $*
$(QUARTUS_BIN)/quartus_fit $*
$(QUARTUS_BIN)/quartus_asm $*
$(QUARTUS_BIN)/quartus_sta $*
%.dep: %.qsf
hdlmake
echo -n "$*.sof $@: $< " > $@.new
echo `grep "set_global_assignment -name [^ ]*_FILE" $< | sed 's/^.*-name .*_FILE//;s/"//g'` >> $@.new
mv $@.new $@
%.jic: %.cof %.sof
$(QUARTUS_BIN)/quartus_cpf -c $<
%.jam: %.jic
$(QUARTUS_BIN)/quartus_cpf -c $< $@
-include $(TARGET).dep
syn/gsi_exploder/wr_core_demo/exploder_top.cof 0 → 100644
View file @ 881d7258
<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
<eprom_name>EPCS128</eprom_name>
<flash_loader_device>EP2AGX125</flash_loader_device>
<output_filename>exploder_top.jic</output_filename>
<n_pages>1</n_pages>
<width>1</width>
<mode>7</mode>
<sof_data>
<user_name>Page_0</user_name>
<page_flags>1</page_flags>
<bit0>
<sof_filename>exploder_top.sof</sof_filename>
</bit0>
</sof_data>
<version>5</version>
<create_cvp_file>0</create_cvp_file>
<options>
<map_file>1</map_file>
</options>
</cof>
syn/gsi_scu/wr_core_demo/Makefile
View file @ 881d7258
......@@ -18,8 +18,9 @@ clean:
$(QUARTUS_BIN)/quartus_sta $*
%.dep: %.qsf
hdlmake
echo -n "$*.sof $@: $< " > $@.new
echo `grep "set_global_assignment -name [^ ]*_FILE" scu.qsf | sed 's/^.*-name .*_FILE//;s/"//g'` >> $@.new
echo `grep "set_global_assignment -name [^ ]*_FILE" $< | sed 's/^.*-name .*_FILE//;s/"//g'` >> $@.new
mv $@.new $@
%.jic: %.cof %.sof
......
syn/gsi_scu/wr_core_demo/scu.qsf
View file @ 881d7258
......@@ -26,11 +26,11 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_Y10 -to nres
set_global_assignment -name SMART_RECOMPILE ON
set_location_assignment PIN_N3 -to clk_20m_vcxo_i
set_location_assignment PIN_AE14 -to clk_20m_vcxo_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_20m_vcxo_i
set_location_assignment PIN_M1 -to clk_125m_pllref_i
set_location_assignment PIN_AE15 -to clk_125m_pllref_i
set_instance_assignment -name IO_STANDARD LVDS -to clk_125m_pllref_i
set_location_assignment PIN_N1 -to "clk_125m_pllref_i(n)"
set_location_assignment PIN_AF15 -to "clk_125m_pllref_i(n)"
set_location_assignment PIN_D15 -to clk_125m_local_i
set_instance_assignment -name IO_STANDARD LVDS -to clk_125m_local_i
set_location_assignment PIN_C15 -to "clk_125m_local_i(n)"
......
top/gsi_exploder/wr_core_demo/exploder_top.sdc
View file @ 881d7258
......@@ -2,13 +2,9 @@ derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
# cut the clock domains from each other
set_clock_groups -asynchronous \
-group { altera_reserved_tck } \
-group { clk_20m_vcxo_i dmtd_clk_pll_inst|* } \
-group { clk_125m_pllref_p sys_pll_inst|* } \
-group { L_CLKp } \
-group { wr_gxb_phy* }
# these paths are supposedly made safe by Tom's sync_ffs. i have my doubts, but ...
set_false_path -from {xwr_core:U_WR_CORE|wr_core:WRPC|xwr_pps_gen:PPS_GEN|wr_pps_gen:WRAPPED_PPSGEN|adj_utc*} \
-to {xwr_core:U_WR_CORE|wr_core:WRPC|xwr_pps_gen:PPS_GEN|wr_pps_gen:WRAPPED_PPSGEN|cntr_utc*}
set_clock_groups -asynchronous \
-group { altera_reserved_tck } \
-group { clk_20m_vcxo_i dmtd_inst|* } \
-group { clk_125m_pllref_i ref_inst|* } \
-group { clk_125m_local_i sys_inst|* } \
-group { wr_gxb_phy* }
top/gsi_scu/wr_core_demo/scu_top.sdc
View file @ 881d7258
......@@ -12,3 +12,7 @@ set_clock_groups -asynchronous \
-group { pcie_refclk_i PCIe|* } \
-group { wr_gxb_phy* } \
-group { LPC_FPGA_CLK }
# PCIe constraints; SERDES Digital Reset inputs are asynchronous:
set_false_path -to {*|altera_pcie_serdes:serdes|*|tx_digitalreset_reg0c[0]}
set_false_path -to {*|altera_pcie_serdes:serdes|*|rx_digitalreset_reg0c[0]}
top/gsi_scu/wr_core_demo/scu_top.vhd
View file @ 881d7258
......@@ -45,8 +45,8 @@ entity scu_top is
-----------------------------------------
-- LEMO on front panel
-----------------------------------------
lemo_io1 : out std_logic_vector(0 downto 0);
lemo_io2 : in std_logic_vector(0 downto 0);
lemo_io1 : inout std_logic;
lemo_io2 : inout std_logic;
lemo_en_in : out std_logic_vector(2 downto 1);
lemo_led : out std_logic_vector(2 downto 1);
......@@ -70,10 +70,16 @@ entity scu_top is
-----------------------------------------------------------------------
OneWire_CB : inout std_logic;
-----------------------------------------------------------------------
-- QL1 serdes
-----------------------------------------------------------------------
-- QL1_GXB_RX : in std_logic_vector(3 downto 0);
-- QL1_GXB_TX : out std_logic_vector(3 downto 0);
-----------------------------------------------------------------------
-- AUX SFP
-----------------------------------------------------------------------
sfp1_tx_disable_o : out std_logic;
sfp1_tx_disable_o : out std_logic := '0';
--sfp1_txp_o : out std_logic;
--sfp1_rxp_i : in std_logic;
......@@ -84,7 +90,7 @@ entity scu_top is
-----------------------------------------------------------------------
-- Timing SFP
-----------------------------------------------------------------------
sfp2_tx_disable_o : out std_logic;
sfp2_tx_disable_o : out std_logic := '0';
sfp2_txp_o : out std_logic;
sfp2_rxp_i : in std_logic;
......@@ -108,6 +114,13 @@ entity scu_top is
A_EXT_LVDS_CLKIN : in std_logic;
EIO : out std_logic_vector(16 downto 0);
-----------------------------------------------------------------------
-- serial channel SCU bus
-----------------------------------------------------------------------
--A_MASTER_CON_RX : in std_logic_vector(3 downto 0);
--A_MASTER_CON_TX : out std_logic_vector(3 downto 0);
-----------------------------------------------------------------------
-- SCU Bus
-----------------------------------------------------------------------
......@@ -145,26 +158,27 @@ entity scu_top is
nWE_FSH : out std_logic;
nOE_FSH : out std_logic;
nRST_FSH : out std_logic;
WAIT_FSH : in std_logic);
WAIT_FSH : in std_logic;
-----------------------------------------------------------------------
-- DDR3
-----------------------------------------------------------------------
-- DDR3_DQ : inout std_logic_vector(15 downto 0);
-- DDR3_DM : out std_logic_vector(1 downto 0);
-- DDR3_BA : out std_logic_vector(2 downto 0);
-- DDR3_ADDR : out std_logic_vector(12 downto 0);
-- DDR3_CS_n : out std_logic_vector(0 downto 0);
DDR3_DQ : inout std_logic_vector(15 downto 0);
DDR3_DM : out std_logic_vector(1 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_ADDR : out std_logic_vector(12 downto 0);
DDR3_CS_n : out std_logic_vector(0 downto 0);
-- DDR3_DQS : inout std_logic_vector(1 downto 0);
-- DDR3_DQSn : inout std_logic_vector(1 downto 0);
-- DDR3_RES_n : out std_logic;
-- DDR3_CKE : out std_logic_vector(0 downto 0);
-- DDR3_ODT : out std_logic_vector(0 downto 0);
-- DDR3_CAS_n : out std_logic;
-- DDR3_RAS_n : out std_logic;
DDR3_RES_n : out std_logic;
DDR3_CKE : out std_logic_vector(0 downto 0);
DDR3_ODT : out std_logic_vector(0 downto 0);
DDR3_CAS_n : out std_logic;
DDR3_RAS_n : out std_logic;
-- DDR3_CLK : inout std_logic_vector(0 downto 0);
-- DDR3_CLK_n : inout std_logic_vector(0 downto 0);
-- DDR3_WE_n : out std_logic);
DDR3_WE_n : out std_logic);
end scu_top;
architecture rtl of scu_top is
......@@ -494,7 +508,7 @@ begin
ref_clk_i => clk_ref,
sys_clk_i => clk_sys,
nRSt_i => rstn_sys,
triggers_i => lemo_io2,
triggers_i(0) => lemo_io2,
tm_time_valid_i => '0',
tm_utc_i => tm_tai,
tm_cycles_i => tm_cycles,
......@@ -564,7 +578,7 @@ begin
sfp2_tx_disable_o <= '0'; -- enable SFP
lemo_en_in <= "01"; -- configure lemo 1 as output, lemo 2 as input
lemo_io1(0) <= ext_pps;
lemo_io1 <= ext_pps;
lemo_led(1) <= ext_pps;
leds_o(0) <= not eca_gpio(0);
......@@ -572,10 +586,10 @@ begin
leds_o(2) <= not eca_gpio(2);
leds_o(3) <= not eca_gpio(3);
-- hpla_ch(0) <= clk_ref;
-- hpla_ch(1) <= clk_sys;
-- hpla_ch(2) <= phy_tx_clk;
-- hpla_ch(3) <= phy_rx_rbclk;
-- hpla_ch(4) <= clk_dmtd;
hpla_ch(0) <= clk_ref;
hpla_ch(1) <= clk_sys;
hpla_ch(2) <= phy_tx_clk;
hpla_ch(3) <= phy_rx_rbclk;
hpla_ch(4) <= clk_dmtd;
end rtl;
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