wrc_core: latest testbench

7c9a35a8 · Tomasz Wlostowski · 3cda6a74 · 7c9a35a8 · 7c9a35a8
Commit 7c9a35a8 authored Oct 26, 2011 by Tomasz Wlostowski
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Showing with 16 additions and 22 deletions

Manifest.py testbench/wrc_core/main_tb/Manifest.py +1 -12

main.sv testbench/wrc_core/main_tb/main.sv +15 -10

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--- a/testbench/wrc_core/main_tb/Manifest.py
+++ b/testbench/wrc_core/main_tb/Manifest.py
@@ -4,18 +4,7 @@ vlog_opt = "+incdir+../../../sim"
 files = [ "main.sv" ]
-modules = { "local" : [ 
+modules = { "local" :  "../../.." }
-        "../../../ip_cores/general-cores",
-        "../../../modules/wr_endpoint",
-        "../../../modules/wr_mini_nic",
-        "../../../modules/wrc_core",
-        "../../../modules/wrc_lm32",
-        "../../../modules/wr_softpll",
-        "../../../modules/wrsw_pps_gen",
-        "../../../modules/timing"
-        ]
-            };
--- a/testbench/wrc_core/main_tb/main.sv
+++ b/testbench/wrc_core/main_tb/main.sv
 `timescale 1ns/1ps
 `include "tbi_utils.sv"
 `include "simdrv_defs.svh"
@@ -71,14 +70,14 @@ module main;
 	.uart_rxd_i       (1'b0),
 	.uart_txd_o       (),
-	.wb_addr_i      (WB.adr[17:0]),
+	.wb_addr_i      (WB.master.adr[17:0]),
-	.wb_data_i      (WB.dat_o),
+	.wb_data_i      (WB.master.dat_o),
-	.wb_data_o      (WB.dat_i),
+	.wb_data_o      (WB.master.dat_i),
 	.wb_sel_i       (4'b1111),
-	.wb_we_i        (WB.we),
+	.wb_we_i        (WB.master.we),
-	.wb_cyc_i       (WB.cyc),
+	.wb_cyc_i       (WB.master.cyc),
-	.wb_stb_i       (WB.stb),
+	.wb_stb_i       (WB.master.stb),
-	.wb_ack_o       (WB.ack),
+	.wb_ack_o       (WB.master.ack),
        .phy_ref_clk_i(clk_ref),
        .phy_tx_data_o(phy_tx_data),
@@ -104,10 +103,16 @@ module main;
   initial begin
+      CWishboneAccessor acc;
      @(posedge rst_n);
      repeat(3) @(posedge clk_sys);
+      acc = WB.get_accessor();
+      acc.write('h62000, 'hffffffff);
+      acc.write('h62000, 0);