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White Rabbit core collection
Commits
77dd337a
Commit
77dd337a
authored
Oct 26, 2011
by
Tomasz Wlostowski
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Plain Diff
wr_core: added legacy conmax interconnect (removed from general-cores)
parent
7c9a35a8
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10 changed files
with
1739 additions
and
0 deletions
+1739
-0
Manifest.py
modules/wrc_core/wb_conmax/Manifest.py
+3
-0
wb_conmax_arb.vhd
modules/wrc_core/wb_conmax/wb_conmax_arb.vhd
+238
-0
wb_conmax_master_if.vhd
modules/wrc_core/wb_conmax/wb_conmax_master_if.vhd
+168
-0
wb_conmax_msel.vhd
modules/wrc_core/wb_conmax/wb_conmax_msel.vhd
+267
-0
wb_conmax_pri_dec.vhd
modules/wrc_core/wb_conmax/wb_conmax_pri_dec.vhd
+91
-0
wb_conmax_pri_enc.vhd
modules/wrc_core/wb_conmax/wb_conmax_pri_enc.vhd
+193
-0
wb_conmax_rf.vhd
modules/wrc_core/wb_conmax/wb_conmax_rf.vhd
+167
-0
wb_conmax_slave_if.vhd
modules/wrc_core/wb_conmax/wb_conmax_slave_if.vhd
+226
-0
wb_conmax_top.vhd
modules/wrc_core/wb_conmax/wb_conmax_top.vhd
+323
-0
wbconmax_pkg.vhd
modules/wrc_core/wb_conmax/wbconmax_pkg.vhd
+63
-0
No files found.
modules/wrc_core/wb_conmax/Manifest.py
0 → 100644
View file @
77dd337a
files
=
[
"wb_conmax_pri_dec.vhd"
,
"wb_conmax_pri_enc.vhd"
,
"wb_conmax_arb.vhd"
,
"wb_conmax_msel.vhd"
,
"wbconmax_pkg.vhd"
,
"wb_conmax_slave_if.vhd"
,
"wb_conmax_master_if.vhd"
,
"wb_conmax_rf.vhd"
,
"wb_conmax_top.vhd"
];
modules/wrc_core/wb_conmax/wb_conmax_arb.vhd
0 → 100644
View file @
77dd337a
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_arb.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2011-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Simple arbiter with round robin. It does not use any prioritization for
-- WB Masters.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
wb_conmax_arb
is
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
--req_i(n) <- wb_cyc from n-th Master
req_i
:
in
std_logic_vector
(
7
downto
0
);
next_i
:
in
std_logic
;
--which master (0 to 7) is granted
gnt_o
:
out
std_logic_vector
(
2
downto
0
)
);
end
wb_conmax_arb
;
architecture
behaviour
of
wb_conmax_arb
is
type
t_arb_states
is
(
GRANT0
,
GRANT1
,
GRANT2
,
GRANT3
,
GRANT4
,
GRANT5
,
GRANT6
,
GRANT7
);
signal
s_state
:
t_arb_states
;
begin
--state transitions
process
(
clk_i
)
begin
if
(
clk_i
'event
and
clk_i
=
'1'
)
then
if
(
rst_i
=
'1'
)
then
s_state
<=
GRANT0
;
else
case
s_state
is
when
GRANT0
=>
--if this req is dropped or next is asserted, check for other req's
if
(
req_i
(
0
)
=
'0'
or
next_i
=
'1'
)
then
if
(
req_i
(
1
)
=
'1'
)
then
s_state
<=
GRANT1
;
elsif
(
req_i
(
2
)
=
'1'
)
then
s_state
<=
GRANT2
;
elsif
(
req_i
(
3
)
=
'1'
)
then
s_state
<=
GRANT3
;
elsif
(
req_i
(
4
)
=
'1'
)
then
s_state
<=
GRANT4
;
elsif
(
req_i
(
5
)
=
'1'
)
then
s_state
<=
GRANT5
;
elsif
(
req_i
(
6
)
=
'1'
)
then
s_state
<=
GRANT6
;
elsif
(
req_i
(
7
)
=
'1'
)
then
s_state
<=
GRANT7
;
end
if
;
end
if
;
when
GRANT1
=>
if
(
req_i
(
1
)
=
'0'
or
next_i
=
'1'
)
then
if
(
req_i
(
2
)
=
'1'
)
then
s_state
<=
GRANT2
;
elsif
(
req_i
(
3
)
=
'1'
)
then
s_state
<=
GRANT3
;
elsif
(
req_i
(
4
)
=
'1'
)
then
s_state
<=
GRANT4
;
elsif
(
req_i
(
5
)
=
'1'
)
then
s_state
<=
GRANT5
;
elsif
(
req_i
(
6
)
=
'1'
)
then
s_state
<=
GRANT6
;
elsif
(
req_i
(
7
)
=
'1'
)
then
s_state
<=
GRANT7
;
elsif
(
req_i
(
0
)
=
'1'
)
then
s_state
<=
GRANT0
;
end
if
;
end
if
;
when
GRANT2
=>
if
(
req_i
(
2
)
=
'0'
or
next_i
=
'1'
)
then
if
(
req_i
(
3
)
=
'1'
)
then
s_state
<=
GRANT3
;
elsif
(
req_i
(
4
)
=
'1'
)
then
s_state
<=
GRANT4
;
elsif
(
req_i
(
5
)
=
'1'
)
then
s_state
<=
GRANT5
;
elsif
(
req_i
(
6
)
=
'1'
)
then
s_state
<=
GRANT6
;
elsif
(
req_i
(
7
)
=
'1'
)
then
s_state
<=
GRANT7
;
elsif
(
req_i
(
0
)
=
'1'
)
then
s_state
<=
GRANT0
;
elsif
(
req_i
(
1
)
=
'1'
)
then
s_state
<=
GRANT1
;
end
if
;
end
if
;
when
GRANT3
=>
if
(
req_i
(
3
)
=
'0'
or
next_i
=
'1'
)
then
if
(
req_i
(
4
)
=
'1'
)
then
s_state
<=
GRANT4
;
elsif
(
req_i
(
5
)
=
'1'
)
then
s_state
<=
GRANT5
;
elsif
(
req_i
(
6
)
=
'1'
)
then
s_state
<=
GRANT6
;
elsif
(
req_i
(
7
)
=
'1'
)
then
s_state
<=
GRANT7
;
elsif
(
req_i
(
0
)
=
'1'
)
then
s_state
<=
GRANT0
;
elsif
(
req_i
(
1
)
=
'1'
)
then
s_state
<=
GRANT1
;
elsif
(
req_i
(
2
)
=
'1'
)
then
s_state
<=
GRANT2
;
end
if
;
end
if
;
when
GRANT4
=>
if
(
req_i
(
4
)
=
'0'
or
next_i
=
'1'
)
then
if
(
req_i
(
5
)
=
'1'
)
then
s_state
<=
GRANT5
;
elsif
(
req_i
(
6
)
=
'1'
)
then
s_state
<=
GRANT6
;
elsif
(
req_i
(
7
)
=
'1'
)
then
s_state
<=
GRANT7
;
elsif
(
req_i
(
0
)
=
'1'
)
then
s_state
<=
GRANT0
;
elsif
(
req_i
(
1
)
=
'1'
)
then
s_state
<=
GRANT1
;
elsif
(
req_i
(
2
)
=
'1'
)
then
s_state
<=
GRANT2
;
elsif
(
req_i
(
3
)
=
'1'
)
then
s_state
<=
GRANT3
;
end
if
;
end
if
;
when
GRANT5
=>
if
(
req_i
(
5
)
=
'0'
or
next_i
=
'1'
)
then
if
(
req_i
(
6
)
=
'1'
)
then
s_state
<=
GRANT6
;
elsif
(
req_i
(
7
)
=
'1'
)
then
s_state
<=
GRANT7
;
elsif
(
req_i
(
0
)
=
'1'
)
then
s_state
<=
GRANT0
;
elsif
(
req_i
(
1
)
=
'1'
)
then
s_state
<=
GRANT1
;
elsif
(
req_i
(
2
)
=
'1'
)
then
s_state
<=
GRANT2
;
elsif
(
req_i
(
3
)
=
'1'
)
then
s_state
<=
GRANT3
;
elsif
(
req_i
(
4
)
=
'1'
)
then
s_state
<=
GRANT4
;
end
if
;
end
if
;
when
GRANT6
=>
if
(
req_i
(
6
)
=
'0'
or
next_i
=
'1'
)
then
if
(
req_i
(
7
)
=
'1'
)
then
s_state
<=
GRANT7
;
elsif
(
req_i
(
0
)
=
'1'
)
then
s_state
<=
GRANT0
;
elsif
(
req_i
(
1
)
=
'1'
)
then
s_state
<=
GRANT1
;
elsif
(
req_i
(
2
)
=
'1'
)
then
s_state
<=
GRANT2
;
elsif
(
req_i
(
3
)
=
'1'
)
then
s_state
<=
GRANT3
;
elsif
(
req_i
(
4
)
=
'1'
)
then
s_state
<=
GRANT4
;
elsif
(
req_i
(
5
)
=
'1'
)
then
s_state
<=
GRANT5
;
end
if
;
end
if
;
when
GRANT7
=>
if
(
req_i
(
7
)
=
'0'
or
next_i
=
'1'
)
then
if
(
req_i
(
0
)
=
'1'
)
then
s_state
<=
GRANT0
;
elsif
(
req_i
(
1
)
=
'1'
)
then
s_state
<=
GRANT1
;
elsif
(
req_i
(
2
)
=
'1'
)
then
s_state
<=
GRANT2
;
elsif
(
req_i
(
3
)
=
'1'
)
then
s_state
<=
GRANT3
;
elsif
(
req_i
(
4
)
=
'1'
)
then
s_state
<=
GRANT4
;
elsif
(
req_i
(
5
)
=
'1'
)
then
s_state
<=
GRANT5
;
elsif
(
req_i
(
6
)
=
'1'
)
then
s_state
<=
GRANT6
;
end
if
;
end
if
;
when
others
=>
s_state
<=
GRANT0
;
end
case
;
end
if
;
end
if
;
end
process
;
process
(
s_state
)
begin
case
(
s_state
)
is
when
GRANT0
=>
gnt_o
<=
"000"
;
when
GRANT1
=>
gnt_o
<=
"001"
;
when
GRANT2
=>
gnt_o
<=
"010"
;
when
GRANT3
=>
gnt_o
<=
"011"
;
when
GRANT4
=>
gnt_o
<=
"100"
;
when
GRANT5
=>
gnt_o
<=
"101"
;
when
GRANT6
=>
gnt_o
<=
"110"
;
when
GRANT7
=>
gnt_o
<=
"111"
;
when
others
=>
gnt_o
<=
"000"
;
end
case
;
end
process
;
end
behaviour
;
modules/wrc_core/wb_conmax/wb_conmax_master_if.vhd
0 → 100644
View file @
77dd337a
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_master_if.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Wishbone interface to connect WB master from outside. Decodes 4 most
-- significant bits of Address bus. Using the selection it multiplexes the
-- Master's WB interface to appropriate Slave interface.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-- 2011-02-16 1.1 greg.d Using generates and types
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
work
;
use
work
.
wbconmax_pkg
.
all
;
entity
wb_conmax_master_if
is
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
--Master interface
wb_master_i
:
in
t_wb_i
;
wb_master_o
:
out
t_wb_o
;
--Slaves(0 to 15) interface
wb_slaves_i
:
in
t_conmax_slaves_i
;
wb_slaves_o
:
out
t_conmax_slaves_o
);
end
wb_conmax_master_if
;
architecture
behaviour
of
wb_conmax_master_if
is
signal
s_slv_sel
:
std_logic_vector
(
3
downto
0
);
signal
s_cyc_o_next
:
std_logic_vector
(
15
downto
0
);
signal
s_cyc_o
:
std_logic_vector
(
15
downto
0
);
begin
--Select logic
s_slv_sel
<=
wb_master_i
.
addr
(
c_aw
-1
downto
c_aw
-4
);
--Address & Data Pass
GEN_OUTS
:
for
I
in
0
to
15
generate
wb_slaves_o
(
I
)
.
addr
<=
wb_master_i
.
addr
;
wb_slaves_o
(
I
)
.
sel
<=
wb_master_i
.
sel
;
wb_slaves_o
(
I
)
.
data
<=
wb_master_i
.
data
;
wb_slaves_o
(
I
)
.
we
<=
wb_master_i
.
we
;
wb_slaves_o
(
I
)
.
cyc
<=
s_cyc_o
(
I
);
wb_slaves_o
(
I
)
.
stb
<=
wb_master_i
.
stb
when
(
s_slv_sel
=
std_logic_vector
(
to_unsigned
(
I
,
4
))
)
else
'0'
;
end
generate
;
wb_master_o
.
data
<=
wb_slaves_i
(
0
)
.
data
when
(
s_slv_sel
=
"0000"
)
else
wb_slaves_i
(
1
)
.
data
when
(
s_slv_sel
=
"0001"
)
else
wb_slaves_i
(
2
)
.
data
when
(
s_slv_sel
=
"0010"
)
else
wb_slaves_i
(
3
)
.
data
when
(
s_slv_sel
=
"0011"
)
else
wb_slaves_i
(
4
)
.
data
when
(
s_slv_sel
=
"0100"
)
else
wb_slaves_i
(
5
)
.
data
when
(
s_slv_sel
=
"0101"
)
else
wb_slaves_i
(
6
)
.
data
when
(
s_slv_sel
=
"0110"
)
else
wb_slaves_i
(
7
)
.
data
when
(
s_slv_sel
=
"0111"
)
else
wb_slaves_i
(
8
)
.
data
when
(
s_slv_sel
=
"1000"
)
else
wb_slaves_i
(
9
)
.
data
when
(
s_slv_sel
=
"1001"
)
else
wb_slaves_i
(
10
)
.
data
when
(
s_slv_sel
=
"1010"
)
else
wb_slaves_i
(
11
)
.
data
when
(
s_slv_sel
=
"1011"
)
else
wb_slaves_i
(
12
)
.
data
when
(
s_slv_sel
=
"1100"
)
else
wb_slaves_i
(
13
)
.
data
when
(
s_slv_sel
=
"1101"
)
else
wb_slaves_i
(
14
)
.
data
when
(
s_slv_sel
=
"1110"
)
else
wb_slaves_i
(
15
)
.
data
when
(
s_slv_sel
=
"1111"
)
else
(
others
=>
'0'
);
--Control Signal Pass
G1
:
for
I
in
0
to
15
generate
s_cyc_o_next
(
I
)
<=
s_cyc_o
(
I
)
when
(
wb_master_i
.
cyc
=
'1'
and
wb_master_i
.
stb
=
'0'
)
else
wb_master_i
.
cyc
when
(
s_slv_sel
=
std_logic_vector
(
to_unsigned
(
I
,
4
))
)
else
'0'
;
end
generate
;
process
(
clk_i
)
begin
if
(
clk_i
'event
and
clk_i
=
'1'
)
then
if
(
rst_i
=
'1'
)
then
s_cyc_o
(
15
downto
0
)
<=
(
others
=>
'0'
);
else
s_cyc_o
(
15
downto
0
)
<=
s_cyc_o_next
(
15
downto
0
);
end
if
;
end
if
;
end
process
;
wb_master_o
.
ack
<=
wb_slaves_i
(
0
)
.
ack
when
(
s_slv_sel
=
"0000"
)
else
wb_slaves_i
(
1
)
.
ack
when
(
s_slv_sel
=
"0001"
)
else
wb_slaves_i
(
2
)
.
ack
when
(
s_slv_sel
=
"0010"
)
else
wb_slaves_i
(
3
)
.
ack
when
(
s_slv_sel
=
"0011"
)
else
wb_slaves_i
(
4
)
.
ack
when
(
s_slv_sel
=
"0100"
)
else
wb_slaves_i
(
5
)
.
ack
when
(
s_slv_sel
=
"0101"
)
else
wb_slaves_i
(
6
)
.
ack
when
(
s_slv_sel
=
"0110"
)
else
wb_slaves_i
(
7
)
.
ack
when
(
s_slv_sel
=
"0111"
)
else
wb_slaves_i
(
8
)
.
ack
when
(
s_slv_sel
=
"1000"
)
else
wb_slaves_i
(
9
)
.
ack
when
(
s_slv_sel
=
"1001"
)
else
wb_slaves_i
(
10
)
.
ack
when
(
s_slv_sel
=
"1010"
)
else
wb_slaves_i
(
11
)
.
ack
when
(
s_slv_sel
=
"1011"
)
else
wb_slaves_i
(
12
)
.
ack
when
(
s_slv_sel
=
"1100"
)
else
wb_slaves_i
(
13
)
.
ack
when
(
s_slv_sel
=
"1101"
)
else
wb_slaves_i
(
14
)
.
ack
when
(
s_slv_sel
=
"1110"
)
else
wb_slaves_i
(
15
)
.
ack
when
(
s_slv_sel
=
"1111"
)
else
'0'
;
wb_master_o
.
err
<=
wb_slaves_i
(
0
)
.
err
when
(
s_slv_sel
=
"0000"
)
else
wb_slaves_i
(
1
)
.
err
when
(
s_slv_sel
=
"0001"
)
else
wb_slaves_i
(
2
)
.
err
when
(
s_slv_sel
=
"0010"
)
else
wb_slaves_i
(
3
)
.
err
when
(
s_slv_sel
=
"0011"
)
else
wb_slaves_i
(
4
)
.
err
when
(
s_slv_sel
=
"0100"
)
else
wb_slaves_i
(
5
)
.
err
when
(
s_slv_sel
=
"0101"
)
else
wb_slaves_i
(
6
)
.
err
when
(
s_slv_sel
=
"0110"
)
else
wb_slaves_i
(
7
)
.
err
when
(
s_slv_sel
=
"0111"
)
else
wb_slaves_i
(
8
)
.
err
when
(
s_slv_sel
=
"1000"
)
else
wb_slaves_i
(
9
)
.
err
when
(
s_slv_sel
=
"1001"
)
else
wb_slaves_i
(
10
)
.
err
when
(
s_slv_sel
=
"1010"
)
else
wb_slaves_i
(
11
)
.
err
when
(
s_slv_sel
=
"1011"
)
else
wb_slaves_i
(
12
)
.
err
when
(
s_slv_sel
=
"1100"
)
else
wb_slaves_i
(
13
)
.
err
when
(
s_slv_sel
=
"1101"
)
else
wb_slaves_i
(
14
)
.
err
when
(
s_slv_sel
=
"1110"
)
else
wb_slaves_i
(
15
)
.
err
when
(
s_slv_sel
=
"1111"
)
else
'0'
;
wb_master_o
.
rty
<=
wb_slaves_i
(
0
)
.
rty
when
(
s_slv_sel
=
"0000"
)
else
wb_slaves_i
(
1
)
.
rty
when
(
s_slv_sel
=
"0001"
)
else
wb_slaves_i
(
2
)
.
rty
when
(
s_slv_sel
=
"0010"
)
else
wb_slaves_i
(
3
)
.
rty
when
(
s_slv_sel
=
"0011"
)
else
wb_slaves_i
(
4
)
.
rty
when
(
s_slv_sel
=
"0100"
)
else
wb_slaves_i
(
5
)
.
rty
when
(
s_slv_sel
=
"0101"
)
else
wb_slaves_i
(
6
)
.
rty
when
(
s_slv_sel
=
"0110"
)
else
wb_slaves_i
(
7
)
.
rty
when
(
s_slv_sel
=
"0111"
)
else
wb_slaves_i
(
8
)
.
rty
when
(
s_slv_sel
=
"1000"
)
else
wb_slaves_i
(
9
)
.
rty
when
(
s_slv_sel
=
"1001"
)
else
wb_slaves_i
(
10
)
.
rty
when
(
s_slv_sel
=
"1010"
)
else
wb_slaves_i
(
11
)
.
rty
when
(
s_slv_sel
=
"1011"
)
else
wb_slaves_i
(
12
)
.
rty
when
(
s_slv_sel
=
"1100"
)
else
wb_slaves_i
(
13
)
.
rty
when
(
s_slv_sel
=
"1101"
)
else
wb_slaves_i
(
14
)
.
rty
when
(
s_slv_sel
=
"1110"
)
else
wb_slaves_i
(
15
)
.
rty
when
(
s_slv_sel
=
"1111"
)
else
'0'
;
end
behaviour
;
modules/wrc_core/wb_conmax/wb_conmax_msel.vhd
0 → 100644
View file @
77dd337a
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_msel.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Prioritizing arbiter for Slave interface. Uses simple arbitrer
-- (wb_conmax_arb) and takes Master's priorities into account.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
wb_conmax_msel
is
generic
(
g_pri_sel
:
integer
:
=
0
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
conf_i
:
in
std_logic_vector
(
15
downto
0
);
req_i
:
in
std_logic_vector
(
7
downto
0
);
next_i
:
in
std_logic
;
sel
:
out
std_logic_vector
(
2
downto
0
)
);
end
wb_conmax_msel
;
architecture
behavioral
of
wb_conmax_msel
is
component
wb_conmax_pri_enc
is
generic
(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel
:
integer
:
=
0
);
port
(
valid_i
:
in
std_logic_vector
(
7
downto
0
);
pri0_i
:
in
std_logic_vector
(
1
downto
0
);
pri1_i
:
in
std_logic_vector
(
1
downto
0
);
pri2_i
:
in
std_logic_vector
(
1
downto
0
);
pri3_i
:
in
std_logic_vector
(
1
downto
0
);
pri4_i
:
in
std_logic_vector
(
1
downto
0
);
pri5_i
:
in
std_logic_vector
(
1
downto
0
);
pri6_i
:
in
std_logic_vector
(
1
downto
0
);
pri7_i
:
in
std_logic_vector
(
1
downto
0
);
pri_o
:
out
std_logic_vector
(
1
downto
0
)
);
end
component
;
component
wb_conmax_arb
is
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
req_i
:
in
std_logic_vector
(
7
downto
0
);
gnt_o
:
out
std_logic_vector
(
2
downto
0
);
next_i
:
in
std_logic
);
end
component
;
signal
s_pri0
,
s_pri1
,
s_pri2
,
s_pri3
,
s_pri4
,
s_pri5
,
s_pri6
,
s_pri7
:
std_logic_vector
(
1
downto
0
);
signal
s_pri_out_d
,
s_pri_out
:
std_logic_vector
(
1
downto
0
);
signal
s_req_p0
,
s_req_p1
,
s_req_p2
,
s_req_p3
:
std_logic_vector
(
7
downto
0
);
signal
s_gnt_p0
,
s_gnt_p1
,
s_gnt_p2
,
s_gnt_p3
:
std_logic_vector
(
2
downto
0
);
signal
s_sel1
,
s_sel2
:
std_logic_vector
(
2
downto
0
);
begin
--------------------------------------
--Priority Select logic
G1
:
if
(
g_pri_sel
=
0
)
generate
s_pri0
<=
"00"
;
s_pri1
<=
"00"
;
s_pri2
<=
"00"
;
s_pri3
<=
"00"
;
s_pri4
<=
"00"
;
s_pri5
<=
"00"
;
s_pri6
<=
"00"
;
s_pri7
<=
"00"
;
end
generate
;
G2
:
if
(
g_pri_sel
=
2
)
generate
s_pri0
<=
conf_i
(
1
downto
0
);
s_pri1
<=
conf_i
(
3
downto
2
);
s_pri2
<=
conf_i
(
5
downto
4
);
s_pri3
<=
conf_i
(
7
downto
6
);
s_pri4
<=
conf_i
(
9
downto
8
);
s_pri5
<=
conf_i
(
11
downto
10
);
s_pri6
<=
conf_i
(
13
downto
12
);
s_pri7
<=
conf_i
(
15
downto
14
);
end
generate
;
G3
:
if
(
g_pri_sel
/=
0
and
g_pri_sel
/=
2
)
generate
s_pri0
<=
'0'
&
conf_i
(
0
);
s_pri1
<=
'0'
&
conf_i
(
2
);
s_pri2
<=
'0'
&
conf_i
(
4
);
s_pri3
<=
'0'
&
conf_i
(
6
);
s_pri4
<=
'0'
&
conf_i
(
8
);
s_pri5
<=
'0'
&
conf_i
(
10
);
s_pri6
<=
'0'
&
conf_i
(
12
);
s_pri7
<=
'0'
&
conf_i
(
14
);
end
generate
;
PRI_ENC
:
wb_conmax_pri_enc
generic
map
(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel
=>
g_pri_sel
)
port
map
(
valid_i
=>
req_i
,
pri0_i
=>
s_pri0
,
pri1_i
=>
s_pri1
,
pri2_i
=>
s_pri2
,
pri3_i
=>
s_pri3
,
pri4_i
=>
s_pri4
,
pri5_i
=>
s_pri5
,
pri6_i
=>
s_pri6
,
pri7_i
=>
s_pri7
,
pri_o
=>
s_pri_out_d
);
process
(
clk_i
)
begin
if
(
clk_i
'event
and
clk_i
=
'1'
)
then
if
(
rst_i
=
'1'
)
then
s_pri_out
<=
"00"
;
elsif
(
next_i
=
'1'
)
then
s_pri_out
<=
s_pri_out_d
;
end
if
;
end
if
;
end
process
;
-----------------------------------------------
--Arbiters
s_req_p0
(
0
)
<=
req_i
(
0
)
when
(
s_pri0
=
"00"
)
else
'0'
;
s_req_p0
(
1
)
<=
req_i
(
1
)
when
(
s_pri1
=
"00"
)
else
'0'
;
s_req_p0
(
2
)
<=
req_i
(
2
)
when
(
s_pri2
=
"00"
)
else
'0'
;
s_req_p0
(
3
)
<=
req_i
(
3
)
when
(
s_pri3
=
"00"
)
else
'0'
;
s_req_p0
(
4
)
<=
req_i
(
4
)
when
(
s_pri4
=
"00"
)
else
'0'
;
s_req_p0
(
5
)
<=
req_i
(
5
)
when
(
s_pri5
=
"00"
)
else
'0'
;
s_req_p0
(
6
)
<=
req_i
(
6
)
when
(
s_pri6
=
"00"
)
else
'0'
;
s_req_p0
(
7
)
<=
req_i
(
7
)
when
(
s_pri7
=
"00"
)
else
'0'
;
s_req_p1
(
0
)
<=
req_i
(
0
)
when
(
s_pri0
=
"01"
)
else
'0'
;
s_req_p1
(
1
)
<=
req_i
(
1
)
when
(
s_pri1
=
"01"
)
else
'0'
;
s_req_p1
(
2
)
<=
req_i
(
2
)
when
(
s_pri2
=
"01"
)
else
'0'
;
s_req_p1
(
3
)
<=
req_i
(
3
)
when
(
s_pri3
=
"01"
)
else
'0'
;
s_req_p1
(
4
)
<=
req_i
(
4
)
when
(
s_pri4
=
"01"
)
else
'0'
;
s_req_p1
(
5
)
<=
req_i
(
5
)
when
(
s_pri5
=
"01"
)
else
'0'
;
s_req_p1
(
6
)
<=
req_i
(
6
)
when
(
s_pri6
=
"01"
)
else
'0'
;
s_req_p1
(
7
)
<=
req_i
(
7
)
when
(
s_pri7
=
"01"
)
else
'0'
;
s_req_p2
(
0
)
<=
req_i
(
0
)
when
(
s_pri0
=
"10"
)
else
'0'
;
s_req_p2
(
1
)
<=
req_i
(
1
)
when
(
s_pri1
=
"10"
)
else
'0'
;
s_req_p2
(
2
)
<=
req_i
(
2
)
when
(
s_pri2
=
"10"
)
else
'0'
;
s_req_p2
(
3
)
<=
req_i
(
3
)
when
(
s_pri3
=
"10"
)
else
'0'
;
s_req_p2
(
4
)
<=
req_i
(
4
)
when
(
s_pri4
=
"10"
)
else
'0'
;
s_req_p2
(
5
)
<=
req_i
(
5
)
when
(
s_pri5
=
"10"
)
else
'0'
;
s_req_p2
(
6
)
<=
req_i
(
6
)
when
(
s_pri6
=
"10"
)
else
'0'
;
s_req_p2
(
7
)
<=
req_i
(
7
)
when
(
s_pri7
=
"10"
)
else
'0'
;
s_req_p3
(
0
)
<=
req_i
(
0
)
when
(
s_pri0
=
"11"
)
else
'0'
;
s_req_p3
(
1
)
<=
req_i
(
1
)
when
(
s_pri1
=
"11"
)
else
'0'
;
s_req_p3
(
2
)
<=
req_i
(
2
)
when
(
s_pri2
=
"11"
)
else
'0'
;
s_req_p3
(
3
)
<=
req_i
(
3
)
when
(
s_pri3
=
"11"
)
else
'0'
;
s_req_p3
(
4
)
<=
req_i
(
4
)
when
(
s_pri4
=
"11"
)
else
'0'
;
s_req_p3
(
5
)
<=
req_i
(
5
)
when
(
s_pri5
=
"11"
)
else
'0'
;
s_req_p3
(
6
)
<=
req_i
(
6
)
when
(
s_pri6
=
"11"
)
else
'0'
;
s_req_p3
(
7
)
<=
req_i
(
7
)
when
(
s_pri7
=
"11"
)
else
'0'
;
ARB0
:
wb_conmax_arb
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
req_i
=>
s_req_p0
,
gnt_o
=>
s_gnt_p0
,
next_i
=>
'0'
);
ARB1
:
wb_conmax_arb
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
req_i
=>
s_req_p1
,
gnt_o
=>
s_gnt_p1
,
next_i
=>
'0'
);
ARB2
:
wb_conmax_arb
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
req_i
=>
s_req_p2
,
gnt_o
=>
s_gnt_p2
,
next_i
=>
'0'
);
ARB3
:
wb_conmax_arb
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
req_i
=>
s_req_p3
,
gnt_o
=>
s_gnt_p3
,
next_i
=>
'0'
);
-----------------------------------------------
--Final Master Select
s_sel1
<=
s_gnt_p1
when
(
s_pri_out
(
0
)
=
'1'
)
else
s_gnt_p0
;
s_sel2
<=
s_gnt_p0
when
(
s_pri_out
=
"00"
)
else
s_gnt_p1
when
(
s_pri_out
=
"01"
)
else
s_gnt_p2
when
(
s_pri_out
=
"10"
)
else
s_gnt_p3
;
G4
:
if
(
g_pri_sel
=
0
)
generate
sel
<=
s_gnt_p0
;
end
generate
;
G5
:
if
(
g_pri_sel
=
1
)
generate
sel
<=
s_sel1
;
end
generate
;
G6
:
if
(
g_pri_sel
/=
0
and
g_pri_sel
/=
1
)
generate
sel
<=
s_sel2
;
end
generate
;
end
behavioral
;
modules/wrc_core/wb_conmax/wb_conmax_pri_dec.vhd
0 → 100644
View file @
77dd337a
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_pri_dec.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Simple Master's priority encoder
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
-- (eg. <if..generate> instead of pri_out_d0 and pri_out_d1)
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
wb_conmax_pri_dec
is
generic
(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel
:
integer
:
=
0
);
port
(
valid_i
:
in
std_logic
;
pri_i
:
in
std_logic_vector
(
1
downto
0
);
pri_o
:
out
std_logic_vector
(
3
downto
0
)
);
end
wb_conmax_pri_dec
;
architecture
behaviour
of
wb_conmax_pri_dec
is
signal
pri_out_d0
:
std_logic_vector
(
3
downto
0
);
signal
pri_out_d1
:
std_logic_vector
(
3
downto
0
);
begin
--4 priority levels
process
(
valid_i
,
pri_i
)
begin
if
(
valid_i
=
'0'
)
then
pri_out_d1
<=
"0001"
;
elsif
(
pri_i
=
"00"
)
then
pri_out_d1
<=
"0001"
;
elsif
(
pri_i
=
"01"
)
then
pri_out_d1
<=
"0010"
;
elsif
(
pri_i
=
"10"
)
then
pri_out_d1
<=
"0100"
;
else
pri_out_d1
<=
"1000"
;
end
if
;
end
process
;
--2 priority levels
process
(
valid_i
,
pri_i
)
begin
if
(
valid_i
=
'0'
)
then
pri_out_d0
<=
"0001"
;
elsif
(
pri_i
=
"00"
)
then
pri_out_d0
<=
"0001"
;
else
pri_out_d0
<=
"0010"
;
end
if
;
end
process
;
--select how many pririty levels
G1
:
if
(
g_pri_sel
=
0
)
generate
pri_o
<=
"0000"
;
end
generate
;
G2
:
if
(
g_pri_sel
=
1
)
generate
pri_o
<=
pri_out_d0
;
end
generate
;
G3
:
if
(
g_pri_sel
/=
0
and
g_pri_sel
/=
1
)
generate
pri_o
<=
pri_out_d1
;
end
generate
;
end
behaviour
;
modules/wrc_core/wb_conmax/wb_conmax_pri_enc.vhd
0 → 100644
View file @
77dd337a
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_pri_enc.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- The set of priority encoders for all Master interfaces.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
wb_conmax_pri_enc
is
generic
(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel
:
integer
:
=
0
);
port
(
valid_i
:
in
std_logic_vector
(
7
downto
0
);
pri0_i
:
in
std_logic_vector
(
1
downto
0
);
pri1_i
:
in
std_logic_vector
(
1
downto
0
);
pri2_i
:
in
std_logic_vector
(
1
downto
0
);
pri3_i
:
in
std_logic_vector
(
1
downto
0
);
pri4_i
:
in
std_logic_vector
(
1
downto
0
);
pri5_i
:
in
std_logic_vector
(
1
downto
0
);
pri6_i
:
in
std_logic_vector
(
1
downto
0
);
pri7_i
:
in
std_logic_vector
(
1
downto
0
);
pri_o
:
out
std_logic_vector
(
1
downto
0
)
);
end
wb_conmax_pri_enc
;
architecture
behaviour
of
wb_conmax_pri_enc
is
component
wb_conmax_pri_dec
is
generic
(
-- :=1 means 2 priority levels, :=2 means 4 priority levels
g_pri_sel
:
integer
:
=
0
);
port
(
valid_i
:
in
std_logic
;
pri_i
:
in
std_logic_vector
(
1
downto
0
);
pri_o
:
out
std_logic_vector
(
3
downto
0
)
);
end
component
;
signal
s_pri0_o
:
std_logic_vector
(
3
downto
0
);
signal
s_pri1_o
:
std_logic_vector
(
3
downto
0
);
signal
s_pri2_o
:
std_logic_vector
(
3
downto
0
);
signal
s_pri3_o
:
std_logic_vector
(
3
downto
0
);
signal
s_pri4_o
:
std_logic_vector
(
3
downto
0
);
signal
s_pri5_o
:
std_logic_vector
(
3
downto
0
);
signal
s_pri6_o
:
std_logic_vector
(
3
downto
0
);
signal
s_pri7_o
:
std_logic_vector
(
3
downto
0
);
signal
s_pritmp_o
:
std_logic_vector
(
3
downto
0
);
signal
s_pri_out0
:
std_logic_vector
(
1
downto
0
);
signal
s_pri_out1
:
std_logic_vector
(
1
downto
0
);
begin
PD0
:
wb_conmax_pri_dec
generic
map
(
g_pri_sel
=>
g_pri_sel
)
port
map
(
valid_i
=>
valid_i
(
0
),
pri_i
=>
pri0_i
,
pri_o
=>
s_pri0_o
);
PD1
:
wb_conmax_pri_dec
generic
map
(
g_pri_sel
=>
g_pri_sel
)
port
map
(
valid_i
=>
valid_i
(
1
),
pri_i
=>
pri1_i
,
pri_o
=>
s_pri1_o
);
PD2
:
wb_conmax_pri_dec
generic
map
(
g_pri_sel
=>
g_pri_sel
)
port
map
(
valid_i
=>
valid_i
(
2
),
pri_i
=>
pri2_i
,
pri_o
=>
s_pri2_o
);
PD3
:
wb_conmax_pri_dec
generic
map
(
g_pri_sel
=>
g_pri_sel
)
port
map
(
valid_i
=>
valid_i
(
3
),
pri_i
=>
pri3_i
,
pri_o
=>
s_pri3_o
);
PD4
:
wb_conmax_pri_dec
generic
map
(
g_pri_sel
=>
g_pri_sel
)
port
map
(
valid_i
=>
valid_i
(
4
),
pri_i
=>
pri4_i
,
pri_o
=>
s_pri4_o
);
PD5
:
wb_conmax_pri_dec
generic
map
(
g_pri_sel
=>
g_pri_sel
)
port
map
(
valid_i
=>
valid_i
(
5
),
pri_i
=>
pri5_i
,
pri_o
=>
s_pri5_o
);
PD6
:
wb_conmax_pri_dec
generic
map
(
g_pri_sel
=>
g_pri_sel
)
port
map
(
valid_i
=>
valid_i
(
6
),
pri_i
=>
pri6_i
,
pri_o
=>
s_pri6_o
);
PD7
:
wb_conmax_pri_dec
generic
map
(
g_pri_sel
=>
g_pri_sel
)
port
map
(
valid_i
=>
valid_i
(
7
),
pri_i
=>
pri7_i
,
pri_o
=>
s_pri7_o
);
s_pritmp_o
<=
s_pri0_o
or
s_pri1_o
or
s_pri2_o
or
s_pri3_o
or
s_pri4_o
or
s_pri5_o
or
s_pri6_o
or
s_pri7_o
;
--4 priority levels
s_pri_out1
<=
"11"
when
(
s_pritmp_o
(
3
)
=
'1'
)
else
"10"
when
(
s_pritmp_o
(
2
)
=
'1'
)
else
"01"
when
(
s_pritmp_o
(
1
)
=
'1'
)
else
"00"
;
--2 priority levels
s_pri_out0
<=
"01"
when
(
s_pritmp_o
(
1
)
=
'1'
)
else
"00"
;
G1
:
if
(
g_pri_sel
=
0
)
generate
pri_o
<=
"00"
;
end
generate
;
G2
:
if
(
g_pri_sel
=
1
)
generate
pri_o
<=
s_pri_out0
;
end
generate
;
G3
:
if
(
g_pri_sel
/=
0
and
g_pri_sel
/=
1
)
generate
pri_o
<=
s_pri_out1
;
end
generate
;
end
behaviour
;
modules/wrc_core/wb_conmax/wb_conmax_rf.vhd
0 → 100644
View file @
77dd337a
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_rf.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Register File - consists of 16 registers. Each stores configuration for
-- different Slave.
-- Each of those 16 registers is the Slave's personal priority register,
-- where the priorities for each Master are stored. The Register File is
-- accessible from Master through Slave 15th interface.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-- 2011-02-16 1.1 greg.d Using generates and types
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
work
;
use
work
.
wbconmax_pkg
.
all
;
entity
wb_conmax_rf
is
generic
(
g_rf_addr
:
integer
range
0
to
15
:
=
15
--0xF
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
--Internal WB interface
int_wb_i
:
in
t_wb_i
;
int_wb_o
:
out
t_wb_o
;
--External WB interface
ext_wb_i
:
in
t_wb_o
;
ext_wb_o
:
out
t_wb_i
;
--Configuration regs
conf_o
:
out
t_rf_conf
);
end
wb_conmax_rf
;
architecture
behaviour
of
wb_conmax_rf
is
signal
s_rf_sel
:
std_logic
;
signal
s_rf_dout
:
std_logic_vector
(
15
downto
0
);
signal
s_rf_ack
:
std_logic
;
signal
s_rf_we
:
std_logic
;
signal
s_conf
:
t_rf_conf
;
signal
s_rf_addr
:
std_logic_vector
(
3
downto
0
);
begin
--Register File select logic
s_rf_addr
<=
std_logic_vector
(
to_unsigned
(
g_rf_addr
,
4
));
s_rf_sel
<=
int_wb_i
.
cyc
and
int_wb_i
.
stb
when
(
int_wb_i
.
addr
(
c_aw
-5
downto
c_aw
-8
)
=
s_rf_addr
)
else
'0'
;
--Register File logic
process
(
clk_i
)
begin
if
(
clk_i
'event
and
clk_i
=
'1'
)
then
s_rf_we
<=
s_rf_sel
and
int_wb_i
.
we
and
not
(
s_rf_we
);
s_rf_ack
<=
s_rf_sel
and
not
(
s_rf_ack
);
end
if
;
end
process
;
--Write logic
process
(
clk_i
)
begin
if
(
clk_i
'event
and
clk_i
=
'1'
)
then
if
(
rst_i
=
'1'
)
then
s_conf
<=
(
others
=>
(
others
=>
'0'
));
elsif
(
s_rf_we
=
'1'
)
then
if
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"0"
)
then
s_conf
(
0
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"1"
)
then
s_conf
(
1
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"2"
)
then
s_conf
(
2
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"3"
)
then
s_conf
(
3
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"4"
)
then
s_conf
(
4
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"5"
)
then
s_conf
(
5
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"6"
)
then
s_conf
(
6
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"7"
)
then
s_conf
(
7
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"8"
)
then
s_conf
(
8
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"9"
)
then
s_conf
(
9
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"a"
)
then
s_conf
(
10
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"b"
)
then
s_conf
(
11
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"c"
)
then
s_conf
(
12
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"d"
)
then
s_conf
(
13
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"e"
)
then
s_conf
(
14
)
<=
int_wb_i
.
data
(
15
downto
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"f"
)
then
s_conf
(
15
)
<=
int_wb_i
.
data
(
15
downto
0
);
end
if
;
end
if
;
end
if
;
end
process
;
--Read logic
process
(
clk_i
)
begin
if
(
clk_i
'event
and
clk_i
=
'1'
)
then
if
(
s_rf_sel
=
'0'
)
then
s_rf_dout
<=
x"0000"
;
else
if
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"0"
)
then
s_rf_dout
<=
s_conf
(
0
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"1"
)
then
s_rf_dout
<=
s_conf
(
1
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"2"
)
then
s_rf_dout
<=
s_conf
(
2
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"3"
)
then
s_rf_dout
<=
s_conf
(
3
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"4"
)
then
s_rf_dout
<=
s_conf
(
4
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"5"
)
then
s_rf_dout
<=
s_conf
(
5
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"6"
)
then
s_rf_dout
<=
s_conf
(
6
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"7"
)
then
s_rf_dout
<=
s_conf
(
7
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"8"
)
then
s_rf_dout
<=
s_conf
(
8
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"9"
)
then
s_rf_dout
<=
s_conf
(
9
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"A"
)
then
s_rf_dout
<=
s_conf
(
10
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"B"
)
then
s_rf_dout
<=
s_conf
(
11
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"C"
)
then
s_rf_dout
<=
s_conf
(
12
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"D"
)
then
s_rf_dout
<=
s_conf
(
13
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"E"
)
then
s_rf_dout
<=
s_conf
(
14
);
elsif
(
int_wb_i
.
addr
(
5
downto
2
)
=
x"F"
)
then
s_rf_dout
<=
s_conf
(
15
);
end
if
;
end
if
;
end
if
;
end
process
;
--Register File bypass logic
ext_wb_o
.
addr
<=
int_wb_i
.
addr
;
ext_wb_o
.
sel
<=
int_wb_i
.
sel
;
ext_wb_o
.
data
<=
int_wb_i
.
data
;
ext_wb_o
.
cyc
<=
int_wb_i
.
cyc
when
(
s_rf_sel
=
'0'
)
else
'0'
;
ext_wb_o
.
stb
<=
int_wb_i
.
stb
;
ext_wb_o
.
we
<=
int_wb_i
.
we
;
int_wb_o
.
data
<=
(
(
c_dw
-1
downto
16
=>
'0'
)
&
s_rf_dout
)
when
(
s_rf_sel
=
'1'
)
else
ext_wb_i
.
data
;
int_wb_o
.
ack
<=
s_rf_ack
when
(
s_rf_sel
=
'1'
)
else
ext_wb_i
.
ack
;
int_wb_o
.
err
<=
'0'
when
(
s_rf_sel
=
'1'
)
else
ext_wb_i
.
err
;
int_wb_o
.
rty
<=
'0'
when
(
s_rf_sel
=
'1'
)
else
ext_wb_i
.
rty
;
conf_o
<=
s_conf
;
end
behaviour
;
modules/wrc_core/wb_conmax/wb_conmax_slave_if.vhd
0 → 100644
View file @
77dd337a
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_slave_if.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Full interface for a single Wishbone Slave. Consists of WB Master interface,
-- Prioritizing Arbiter and multiplexer for selecting appropriate Master.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-- 2011-02-16 1.1 greg.d Using generates and types
-------------------------------------------------------------------------------
-- TODO:
-- Code optimization. (now it is more like dummy translation from Verilog)
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
work
;
use
work
.
wbconmax_pkg
.
all
;
entity
wb_conmax_slave_if
is
generic
(
g_pri_sel
:
integer
:
=
2
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
conf_i
:
in
std_logic_vector
(
15
downto
0
);
--Slave interface
wb_slave_i
:
in
t_wb_o
;
wb_slave_o
:
out
t_wb_i
;
--Master (0 to 7) interfaces
wb_masters_i
:
in
t_conmax_masters_i
;
wb_masters_o
:
out
t_conmax_masters_o
);
end
wb_conmax_slave_if
;
architecture
bahaviour
of
wb_conmax_slave_if
is
component
wb_conmax_arb
is
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
req_i
:
in
std_logic_vector
(
7
downto
0
);
gnt_o
:
out
std_logic_vector
(
2
downto
0
);
next_i
:
in
std_logic
);
end
component
;
component
wb_conmax_msel
is
generic
(
g_pri_sel
:
integer
:
=
0
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
conf_i
:
in
std_logic_vector
(
15
downto
0
);
req_i
:
in
std_logic_vector
(
7
downto
0
);
next_i
:
in
std_logic
;
sel
:
out
std_logic_vector
(
2
downto
0
)
);
end
component
;
signal
s_wb_cyc_o
:
std_logic
;
signal
s_msel_simple
,
s_msel_pe
,
s_msel
:
std_logic_vector
(
2
downto
0
);
signal
s_next
:
std_logic
;
signal
s_mcyc
:
std_logic_vector
(
7
downto
0
);
signal
s_arb_req_i
:
std_logic_vector
(
7
downto
0
);
begin
wb_slave_o
.
cyc
<=
s_wb_cyc_o
;
process
(
clk_i
)
begin
if
(
clk_i
'event
and
clk_i
=
'1'
)
then
s_next
<=
not
(
s_wb_cyc_o
);
end
if
;
end
process
;
s_arb_req_i
<=
wb_masters_i
(
7
)
.
cyc
&
wb_masters_i
(
6
)
.
cyc
&
wb_masters_i
(
5
)
.
cyc
&
wb_masters_i
(
4
)
.
cyc
&
wb_masters_i
(
3
)
.
cyc
&
wb_masters_i
(
2
)
.
cyc
&
wb_masters_i
(
1
)
.
cyc
&
wb_masters_i
(
0
)
.
cyc
;
--Prioritizing Arbiter
ARB
:
wb_conmax_arb
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
req_i
=>
s_arb_req_i
,
gnt_o
=>
s_msel_simple
,
next_i
=>
'0'
--no round robin
);
MSEL
:
wb_conmax_msel
generic
map
(
g_pri_sel
=>
g_pri_sel
)
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
conf_i
=>
conf_i
,
req_i
=>
s_arb_req_i
,
next_i
=>
s_next
,
sel
=>
s_msel_pe
);
G1
:
if
(
g_pri_sel
=
0
)
generate
s_msel
<=
s_msel_simple
;
end
generate
;
G2
:
if
(
g_pri_sel
/=
0
)
generate
s_msel
<=
s_msel_pe
;
end
generate
;
-------------------------------------
--Address & Data Pass
wb_slave_o
.
addr
<=
wb_masters_i
(
0
)
.
addr
when
(
s_msel
=
"000"
)
else
wb_masters_i
(
1
)
.
addr
when
(
s_msel
=
"001"
)
else
wb_masters_i
(
2
)
.
addr
when
(
s_msel
=
"010"
)
else
wb_masters_i
(
3
)
.
addr
when
(
s_msel
=
"011"
)
else
wb_masters_i
(
4
)
.
addr
when
(
s_msel
=
"100"
)
else
wb_masters_i
(
5
)
.
addr
when
(
s_msel
=
"101"
)
else
wb_masters_i
(
6
)
.
addr
when
(
s_msel
=
"110"
)
else
wb_masters_i
(
7
)
.
addr
when
(
s_msel
=
"111"
)
else
(
others
=>
'0'
);
wb_slave_o
.
sel
<=
wb_masters_i
(
0
)
.
sel
when
(
s_msel
=
"000"
)
else
wb_masters_i
(
1
)
.
sel
when
(
s_msel
=
"001"
)
else
wb_masters_i
(
2
)
.
sel
when
(
s_msel
=
"010"
)
else
wb_masters_i
(
3
)
.
sel
when
(
s_msel
=
"011"
)
else
wb_masters_i
(
4
)
.
sel
when
(
s_msel
=
"100"
)
else
wb_masters_i
(
5
)
.
sel
when
(
s_msel
=
"101"
)
else
wb_masters_i
(
6
)
.
sel
when
(
s_msel
=
"110"
)
else
wb_masters_i
(
7
)
.
sel
when
(
s_msel
=
"111"
)
else
(
others
=>
'0'
);
wb_slave_o
.
data
<=
wb_masters_i
(
0
)
.
data
when
(
s_msel
=
"000"
)
else
wb_masters_i
(
1
)
.
data
when
(
s_msel
=
"001"
)
else
wb_masters_i
(
2
)
.
data
when
(
s_msel
=
"010"
)
else
wb_masters_i
(
3
)
.
data
when
(
s_msel
=
"011"
)
else
wb_masters_i
(
4
)
.
data
when
(
s_msel
=
"100"
)
else
wb_masters_i
(
5
)
.
data
when
(
s_msel
=
"101"
)
else
wb_masters_i
(
6
)
.
data
when
(
s_msel
=
"110"
)
else
wb_masters_i
(
7
)
.
data
when
(
s_msel
=
"111"
)
else
(
others
=>
'0'
);
G_OUT
:
for
I
in
0
to
7
generate
wb_masters_o
(
I
)
.
data
<=
wb_slave_i
.
data
;
wb_masters_o
(
I
)
.
ack
<=
wb_slave_i
.
ack
when
(
s_msel
=
std_logic_vector
(
to_unsigned
(
I
,
3
))
)
else
'0'
;
wb_masters_o
(
I
)
.
err
<=
wb_slave_i
.
err
when
(
s_msel
=
std_logic_vector
(
to_unsigned
(
I
,
3
))
)
else
'0'
;
wb_masters_o
(
I
)
.
rty
<=
wb_slave_i
.
rty
when
(
s_msel
=
std_logic_vector
(
to_unsigned
(
I
,
3
))
)
else
'0'
;
end
generate
;
------------------------------------
--Control Signal Pass
wb_slave_o
.
we
<=
wb_masters_i
(
0
)
.
we
when
(
s_msel
=
"000"
)
else
wb_masters_i
(
1
)
.
we
when
(
s_msel
=
"001"
)
else
wb_masters_i
(
2
)
.
we
when
(
s_msel
=
"010"
)
else
wb_masters_i
(
3
)
.
we
when
(
s_msel
=
"011"
)
else
wb_masters_i
(
4
)
.
we
when
(
s_msel
=
"100"
)
else
wb_masters_i
(
5
)
.
we
when
(
s_msel
=
"101"
)
else
wb_masters_i
(
6
)
.
we
when
(
s_msel
=
"110"
)
else
wb_masters_i
(
7
)
.
we
when
(
s_msel
=
"111"
)
else
'0'
;
process
(
clk_i
)
begin
if
(
clk_i
'event
and
clk_i
=
'1'
)
then
s_mcyc
(
7
downto
0
)
<=
wb_masters_i
(
7
)
.
cyc
&
wb_masters_i
(
6
)
.
cyc
&
wb_masters_i
(
5
)
.
cyc
&
wb_masters_i
(
4
)
.
cyc
&
wb_masters_i
(
3
)
.
cyc
&
wb_masters_i
(
2
)
.
cyc
&
wb_masters_i
(
1
)
.
cyc
&
wb_masters_i
(
0
)
.
cyc
;
end
if
;
end
process
;
s_wb_cyc_o
<=
wb_masters_i
(
0
)
.
cyc
and
s_mcyc
(
0
)
when
(
s_msel
=
"000"
)
else
wb_masters_i
(
1
)
.
cyc
and
s_mcyc
(
1
)
when
(
s_msel
=
"001"
)
else
wb_masters_i
(
2
)
.
cyc
and
s_mcyc
(
2
)
when
(
s_msel
=
"010"
)
else
wb_masters_i
(
3
)
.
cyc
and
s_mcyc
(
3
)
when
(
s_msel
=
"011"
)
else
wb_masters_i
(
4
)
.
cyc
and
s_mcyc
(
4
)
when
(
s_msel
=
"100"
)
else
wb_masters_i
(
5
)
.
cyc
and
s_mcyc
(
5
)
when
(
s_msel
=
"101"
)
else
wb_masters_i
(
6
)
.
cyc
and
s_mcyc
(
6
)
when
(
s_msel
=
"110"
)
else
wb_masters_i
(
7
)
.
cyc
and
s_mcyc
(
7
)
when
(
s_msel
=
"111"
)
else
'0'
;
wb_slave_o
.
stb
<=
wb_masters_i
(
0
)
.
stb
when
(
s_msel
=
"000"
)
else
wb_masters_i
(
1
)
.
stb
when
(
s_msel
=
"001"
)
else
wb_masters_i
(
2
)
.
stb
when
(
s_msel
=
"010"
)
else
wb_masters_i
(
3
)
.
stb
when
(
s_msel
=
"011"
)
else
wb_masters_i
(
4
)
.
stb
when
(
s_msel
=
"100"
)
else
wb_masters_i
(
5
)
.
stb
when
(
s_msel
=
"101"
)
else
wb_masters_i
(
6
)
.
stb
when
(
s_msel
=
"110"
)
else
wb_masters_i
(
7
)
.
stb
when
(
s_msel
=
"111"
)
else
'0'
;
end
bahaviour
;
modules/wrc_core/wb_conmax/wb_conmax_top.vhd
0 → 100644
View file @
77dd337a
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_conmax_top.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
-- Last update: 2010-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Wishbone Interconnect Matrix, up to 8 Masters and 16 Slaves. Features
-- prioritized arbiter inside each Slave Interface (1, 2 of 4 priority levels).
-- Allows the parallel communication between masters and slaves on
-- different interfaces.
-- It is the WISHBONE Conmax IP Core from opencores.org rewritten in VHDL (from
-- Verilog) with some code optimalization.
--
-------------------------------------------------------------------------------
-- Copyright (C) 2000-2002 Rudolf Usselmann
-- Copyright (c) 2011 Grzegorz Daniluk (VHDL port)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-12 1.0 greg.d Created
-- 2011-02-16 1.1 greg.d Using generates and types
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
library
work
;
use
work
.
wbconmax_pkg
.
all
;
entity
wb_conmax_top
is
generic
(
g_rf_addr
:
integer
range
0
to
15
:
=
15
--0xf
);
port
(
clk_i
:
std_logic
;
rst_i
:
std_logic
;
wb_masters_i
:
in
t_conmax_masters_i
;
wb_masters_o
:
out
t_conmax_masters_o
;
wb_slaves_i
:
in
t_conmax_slaves_i
;
wb_slaves_o
:
out
t_conmax_slaves_o
);
end
wb_conmax_top
;
architecture
struct
of
wb_conmax_top
is
component
wb_conmax_master_if
is
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
--Master interface
wb_master_i
:
in
t_wb_i
;
wb_master_o
:
out
t_wb_o
;
--Slaves(0 to 15) interface
wb_slaves_i
:
in
t_conmax_slaves_i
;
wb_slaves_o
:
out
t_conmax_slaves_o
);
end
component
;
component
wb_conmax_slave_if
is
generic
(
g_pri_sel
:
integer
:
=
2
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
conf_i
:
in
std_logic_vector
(
15
downto
0
);
--Slave interface
wb_slave_i
:
in
t_wb_o
;
wb_slave_o
:
out
t_wb_i
;
--Master (0 to 7) interfaces
wb_masters_i
:
in
t_conmax_masters_i
;
wb_masters_o
:
out
t_conmax_masters_o
);
end
component
;
component
wb_conmax_rf
is
generic
(
g_rf_addr
:
integer
range
0
to
15
:
=
15
--0xF
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
--Internal WB interface
int_wb_i
:
in
t_wb_i
;
int_wb_o
:
out
t_wb_o
;
--External WB interface
ext_wb_i
:
in
t_wb_o
;
ext_wb_o
:
out
t_wb_i
;
--Configuration regs
conf_o
:
out
t_rf_conf
);
end
component
;
signal
intwb_s15_i
:
t_wb_o
;
signal
intwb_s15_o
:
t_wb_i
;
--M0Sx
signal
m0_slaves_i
:
t_conmax_slaves_i
;
signal
m0_slaves_o
:
t_conmax_slaves_o
;
signal
m1_slaves_i
:
t_conmax_slaves_i
;
signal
m1_slaves_o
:
t_conmax_slaves_o
;
signal
m2_slaves_i
:
t_conmax_slaves_i
;
signal
m2_slaves_o
:
t_conmax_slaves_o
;
signal
m3_slaves_i
:
t_conmax_slaves_i
;
signal
m3_slaves_o
:
t_conmax_slaves_o
;
signal
m4_slaves_i
:
t_conmax_slaves_i
;
signal
m4_slaves_o
:
t_conmax_slaves_o
;
signal
m5_slaves_i
:
t_conmax_slaves_i
;
signal
m5_slaves_o
:
t_conmax_slaves_o
;
signal
m6_slaves_i
:
t_conmax_slaves_i
;
signal
m6_slaves_o
:
t_conmax_slaves_o
;
signal
m7_slaves_i
:
t_conmax_slaves_i
;
signal
m7_slaves_o
:
t_conmax_slaves_o
;
signal
s_conf
:
t_rf_conf
;
signal
s15_wb_masters_i
:
t_conmax_masters_i
;
signal
s15_wb_masters_o
:
t_conmax_masters_o
;
begin
--Master interfaces
M0
:
wb_conmax_master_if
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
--Master interface
wb_master_i
=>
wb_masters_i
(
0
),
wb_master_o
=>
wb_masters_o
(
0
),
--Slaves(0 to 15) interface
wb_slaves_i
=>
m0_slaves_i
,
wb_slaves_o
=>
m0_slaves_o
);
M1
:
wb_conmax_master_if
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
wb_master_i
=>
wb_masters_i
(
1
),
wb_master_o
=>
wb_masters_o
(
1
),
wb_slaves_i
=>
m1_slaves_i
,
wb_slaves_o
=>
m1_slaves_o
);
M2
:
wb_conmax_master_if
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
wb_master_i
=>
wb_masters_i
(
2
),
wb_master_o
=>
wb_masters_o
(
2
),
wb_slaves_i
=>
m2_slaves_i
,
wb_slaves_o
=>
m2_slaves_o
);
M3
:
wb_conmax_master_if
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
wb_master_i
=>
wb_masters_i
(
3
),
wb_master_o
=>
wb_masters_o
(
3
),
wb_slaves_i
=>
m3_slaves_i
,
wb_slaves_o
=>
m3_slaves_o
);
M4
:
wb_conmax_master_if
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
wb_master_i
=>
wb_masters_i
(
4
),
wb_master_o
=>
wb_masters_o
(
4
),
wb_slaves_i
=>
m4_slaves_i
,
wb_slaves_o
=>
m4_slaves_o
);
M5
:
wb_conmax_master_if
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
wb_master_i
=>
wb_masters_i
(
5
),
wb_master_o
=>
wb_masters_o
(
5
),
wb_slaves_i
=>
m5_slaves_i
,
wb_slaves_o
=>
m5_slaves_o
);
M6
:
wb_conmax_master_if
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
wb_master_i
=>
wb_masters_i
(
6
),
wb_master_o
=>
wb_masters_o
(
6
),
wb_slaves_i
=>
m6_slaves_i
,
wb_slaves_o
=>
m6_slaves_o
);
M7
:
wb_conmax_master_if
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
wb_master_i
=>
wb_masters_i
(
7
),
wb_master_o
=>
wb_masters_o
(
7
),
wb_slaves_i
=>
m7_slaves_i
,
wb_slaves_o
=>
m7_slaves_o
);
--------------------------------------------------
--Slave interfaces
S_GEN
:
for
I
in
0
to
14
generate
SLV
:
wb_conmax_slave_if
generic
map
(
g_pri_sel
=>
g_pri_sel
(
I
)
)
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
conf_i
=>
s_conf
(
I
),
--Slave interface
wb_slave_i
=>
wb_slaves_i
(
I
),
wb_slave_o
=>
wb_slaves_o
(
I
),
--Interfaces to masters
wb_masters_i
(
0
)
=>
m0_slaves_o
(
I
),
wb_masters_i
(
1
)
=>
m1_slaves_o
(
I
),
wb_masters_i
(
2
)
=>
m2_slaves_o
(
I
),
wb_masters_i
(
3
)
=>
m3_slaves_o
(
I
),
wb_masters_i
(
4
)
=>
m4_slaves_o
(
I
),
wb_masters_i
(
5
)
=>
m5_slaves_o
(
I
),
wb_masters_i
(
6
)
=>
m6_slaves_o
(
I
),
wb_masters_i
(
7
)
=>
m7_slaves_o
(
I
),
wb_masters_o
(
0
)
=>
m0_slaves_i
(
I
),
wb_masters_o
(
1
)
=>
m1_slaves_i
(
I
),
wb_masters_o
(
2
)
=>
m2_slaves_i
(
I
),
wb_masters_o
(
3
)
=>
m3_slaves_i
(
I
),
wb_masters_o
(
4
)
=>
m4_slaves_i
(
I
),
wb_masters_o
(
5
)
=>
m5_slaves_i
(
I
),
wb_masters_o
(
6
)
=>
m6_slaves_i
(
I
),
wb_masters_o
(
7
)
=>
m7_slaves_i
(
I
)
);
end
generate
;
s15_wb_masters_i
(
0
)
<=
m0_slaves_o
(
15
);
s15_wb_masters_i
(
1
)
<=
m1_slaves_o
(
15
);
s15_wb_masters_i
(
2
)
<=
m2_slaves_o
(
15
);
s15_wb_masters_i
(
3
)
<=
m3_slaves_o
(
15
);
s15_wb_masters_i
(
4
)
<=
m4_slaves_o
(
15
);
s15_wb_masters_i
(
5
)
<=
m5_slaves_o
(
15
);
s15_wb_masters_i
(
6
)
<=
m6_slaves_o
(
15
);
s15_wb_masters_i
(
7
)
<=
m7_slaves_o
(
15
);
m0_slaves_i
(
15
)
<=
s15_wb_masters_o
(
0
);
m1_slaves_i
(
15
)
<=
s15_wb_masters_o
(
1
);
m2_slaves_i
(
15
)
<=
s15_wb_masters_o
(
2
);
m3_slaves_i
(
15
)
<=
s15_wb_masters_o
(
3
);
m4_slaves_i
(
15
)
<=
s15_wb_masters_o
(
4
);
m5_slaves_i
(
15
)
<=
s15_wb_masters_o
(
5
);
m6_slaves_i
(
15
)
<=
s15_wb_masters_o
(
6
);
m7_slaves_i
(
15
)
<=
s15_wb_masters_o
(
7
);
SLV15
:
wb_conmax_slave_if
generic
map
(
g_pri_sel
=>
g_pri_sel
(
15
)
)
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
conf_i
=>
s_conf
(
15
),
--Slave interface
wb_slave_i
=>
intwb_s15_i
,
wb_slave_o
=>
intwb_s15_o
,
--Interfaces to masters
wb_masters_i
=>
s15_wb_masters_i
,
wb_masters_o
=>
s15_wb_masters_o
);
---------------------------------------
--Register File
RF
:
wb_conmax_rf
generic
map
(
g_rf_addr
=>
g_rf_addr
)
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
int_wb_i
=>
intwb_s15_o
,
int_wb_o
=>
intwb_s15_i
,
ext_wb_i
=>
wb_slaves_i
(
15
),
ext_wb_o
=>
wb_slaves_o
(
15
),
conf_o
=>
s_conf
);
end
struct
;
modules/wrc_core/wb_conmax/wbconmax_pkg.vhd
0 → 100644
View file @
77dd337a
-------------------------------------------------------------------------------
-- Title : Wishbone interconnect matrix for WR Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wbconmax_pkg.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-16
-- Last update: 2010-02-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Package for WB interconnect matrix. Defines basic constants and types used
-- to simplify WB interface connections.
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-16 1.1 greg.d Using generates and types
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
package
wbconmax_pkg
is
type
t_rf_conf
is
array
(
0
to
15
)
of
std_logic_vector
(
15
downto
0
);
constant
c_dw
:
integer
:
=
32
;
--data width
constant
c_aw
:
integer
:
=
18
;
--address width = max 14b (for dpram) + 4b
--for wb_intercom (Mst selects Slave)
constant
c_sw
:
integer
:
=
4
;
-- c_dw/8
--g_pri_selx := 0 (1 priority level), 1 (2 pri levels) or 2 (4 pri levels).
type
t_pri_sels
is
array
(
0
to
15
)
of
integer
range
0
to
3
;
constant
g_pri_sel
:
t_pri_sels
:
=
(
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
,
2
);
--as in original WB conmax spec and implementation, those are
--inputs fed by WB Master from outside
type
t_wb_i
is
record
data
:
std_logic_vector
(
c_dw
-1
downto
0
);
addr
:
std_logic_vector
(
c_aw
-1
downto
0
);
sel
:
std_logic_vector
(
c_sw
-1
downto
0
);
we
:
std_logic
;
cyc
:
std_logic
;
stb
:
std_logic
;
end
record
;
type
t_wb_o
is
record
data
:
std_logic_vector
(
c_dw
-1
downto
0
);
ack
:
std_logic
;
err
:
std_logic
;
rty
:
std_logic
;
end
record
;
type
t_conmax_masters_i
is
array
(
0
to
7
)
of
t_wb_i
;
type
t_conmax_masters_o
is
array
(
0
to
7
)
of
t_wb_o
;
type
t_conmax_slaves_i
is
array
(
0
to
15
)
of
t_wb_o
;
type
t_conmax_slaves_o
is
array
(
0
to
15
)
of
t_wb_i
;
end
wbconmax_pkg
;
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