minic: add a register to report TX timestamp readiness

After transmitting a frame in software, the LM32 reads out the timestamp set by hardware. Naturally, this comes after the frame has been sent, so the LM32 must wait. Prior to this patch the only thing it could wait for was DMA idle. However, DMA of the packet completes before the timestamp is ready. Thus there was a race condition where the LM32 would see an old TS.

minic: add a register to report TX timestamp readiness
After transmitting a frame in software, the LM32 reads out the timestamp set by hardware. Naturally, this comes after the frame has been sent, so the LM32 must wait. Prior to this patch the only thing it could wait for was DMA idle. However, DMA of the packet completes before the timestamp is ready. Thus there was a race condition where the LM32 would see an old TS.
763b7594 · Wesley W. Terpstra · 330484fe · 763b7594 · 763b7594 · 763b7594
Commit 763b7594 authored Mar 07, 2013 by Wesley W. Terpstra
5 changed files
--- a/modules/wr_mini_nic/mini_nic.wb
+++ b/modules/wr_mini_nic/mini_nic.wb
@@ -64,6 +64,15 @@ peripheral {
       access_dev = READ_ONLY;
    };

+			field {
+				 name = "TX TS ready";
+				 prefix = "TX_TS_READY";
+				 description = "1: the TX transfer is complete and a timestamp is available";
+				 type = BIT;
+				 access_bus = READ_ONLY;
+				 access_dev = WRITE_ONLY;
+			};
+
    field {
       name = "RX Accepted Packet Classes";
       prefix = "RX_CLASS";

--- a/modules/wr_mini_nic/minic_wb_slave.vhd
+++ b/modules/wr_mini_nic/minic_wb_slave.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : minic_wb_slave.vhd
 -- Author         : auto-generated by wbgen2 from mini_nic.wb
-- Created        : Thu Feb 14 10:46:27 2013
+-- Created        : Thu Mar  7 14:45:52 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
@@ -139,13 +139,13 @@ begin
            rddata_reg(8) <= regs_i.mcr_rx_ready_i;
            rddata_reg(9) <= regs_i.mcr_rx_full_i;
            rddata_reg(10) <= minic_mcr_rx_en_int;
+            rddata_reg(11) <= regs_i.mcr_tx_ts_ready_i;
            rddata_reg(23 downto 16) <= minic_mcr_rx_class_int;
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
-            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
@@ -447,6 +447,7 @@ begin
 -- RX DMA buffer full
 -- RX DMA enable
  regs_o.mcr_rx_en_o <= minic_mcr_rx_en_int;
+-- TX TS ready
 -- RX Accepted Packet Classes
  regs_o.mcr_rx_class_o <= minic_mcr_rx_class_int;
 -- TX DMA buffer address

--- a/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
+++ b/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : minic_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from mini_nic.wb
-- Created        : Thu Feb 14 10:46:27 2013
+-- Created        : Thu Mar  7 14:45:52 2013
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
@@ -25,6 +25,7 @@ package minic_wbgen2_pkg is
    mcr_tx_error_i                           : std_logic;
    mcr_rx_ready_i                           : std_logic;
    mcr_rx_full_i                            : std_logic;
+    mcr_tx_ts_ready_i                        : std_logic;
    tx_addr_i                                : std_logic_vector(23 downto 0);
    rx_addr_i                                : std_logic_vector(23 downto 0);
    rx_size_i                                : std_logic_vector(23 downto 0);
@@ -42,6 +43,7 @@ package minic_wbgen2_pkg is
    mcr_tx_error_i => '0',
    mcr_rx_ready_i => '0',
    mcr_rx_full_i => '0',
+    mcr_tx_ts_ready_i => '0',
    tx_addr_i => (others => '0'),
    rx_addr_i => (others => '0'),
    rx_size_i => (others => '0'),
@@ -120,6 +122,7 @@ tmp.mcr_tx_idle_i := f_x_to_zero(left.mcr_tx_idle_i) or f_x_to_zero(right.mcr_tx
 tmp.mcr_tx_error_i := f_x_to_zero(left.mcr_tx_error_i) or f_x_to_zero(right.mcr_tx_error_i);
 tmp.mcr_rx_ready_i := f_x_to_zero(left.mcr_rx_ready_i) or f_x_to_zero(right.mcr_rx_ready_i);
 tmp.mcr_rx_full_i := f_x_to_zero(left.mcr_rx_full_i) or f_x_to_zero(right.mcr_rx_full_i);
+tmp.mcr_tx_ts_ready_i := f_x_to_zero(left.mcr_tx_ts_ready_i) or f_x_to_zero(right.mcr_tx_ts_ready_i);
 tmp.tx_addr_i := f_x_to_zero(left.tx_addr_i) or f_x_to_zero(right.tx_addr_i);
 tmp.rx_addr_i := f_x_to_zero(left.rx_addr_i) or f_x_to_zero(right.rx_addr_i);
 tmp.rx_size_i := f_x_to_zero(left.rx_size_i) or f_x_to_zero(right.rx_size_i);

--- a/modules/wr_mini_nic/wr_mini_nic.vhd
+++ b/modules/wr_mini_nic/wr_mini_nic.vhd
@@ -1051,7 +1051,7 @@ begin  -- behavioral
  begin
    if rising_edge(clk_sys_i) then
      if(rst_n_i = '0') then
-
+        regs_in.mcr_tx_ts_ready_i <= '0';
        regs_in.tsr0_valid_i <= '0';
        regs_in.tsr0_pid_i   <= (others => '0');
        regs_in.tsr0_fid_i   <= (others => '0');
@@ -1061,12 +1061,15 @@ begin  -- behavioral
        -- Make sure the timestamp is written to the FIFO only once.

        if(txtsu_stb_i = '1' and txtsu_ack_int = '0') then
+          regs_in.mcr_tx_ts_ready_i <= '1';
          regs_in.tsr0_valid_i <= not txtsu_tsincorrect_i;
          regs_in.tsr0_fid_i   <= txtsu_frame_id_i;
          regs_in.tsr0_pid_i   <= txtsu_port_id_i;
          regs_in.tsr1_tsval_i <= txtsu_tsval_i;
          txtsu_ack_int        <= '1';
        else
+          -- clear the TS ready flag when a transmission begins
+          regs_in.mcr_tx_ts_ready_i <= regs_in.mcr_tx_ts_ready_i and regs_in.mcr_tx_idle_i;
          txtsu_ack_int <= '0';
        end if;
      end if;

--- a/sim/minic_regs.vh
+++ b/sim/minic_regs.vh
@@ -11,6 +11,8 @@
 `define MINIC_MCR_RX_FULL 32'h00000200
 `define MINIC_MCR_RX_EN_OFFSET 10
 `define MINIC_MCR_RX_EN 32'h00000400
+`define MINIC_MCR_TX_TS_READY_OFFSET 11
+`define MINIC_MCR_TX_TS_READY 32'h00000800
 `define MINIC_MCR_RX_CLASS_OFFSET 16
 `define MINIC_MCR_RX_CLASS 32'h00ff0000
 `define ADDR_MINIC_TX_ADDR             7'h4