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White Rabbit core collection
Commit 71f67994 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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minic:wip

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modules/wr_endpoint/Manifest.py
View file @ 71f67994
files = [ "endpoint_private_pkg.vhd",
"ep_rx_pcs_8bit.vhd",
"ep_tx_pcs_8bit.vhd",
"ep_tx_pcs_16bit.vhd",
"ep_rx_pcs_16bit.vhd",
"ep_autonegotiation.vhd",
"ep_pcs_tbi_mdio_wb.vhd",
"ep_1000basex_pcs_8bit.vhd",
"ep_1000basex_pcs.vhd",
"ep_rx_crc_size_check.vhd",
"ep_rx_bypass_queue.vhd",
"ep_rx_path.vhd",
......@@ -14,13 +16,17 @@ files = [ "endpoint_private_pkg.vhd",
"ep_tx_framer.vhd",
"ep_packet_filter.vhd",
"ep_rx_vlan_unit.vhd",
# "ep_flow_control.vhd",
"ep_ts_counter.vhd",
"ep_rx_status_reg_insert.vhd",
"ep_timestamping_unit.vhd",
# "ep_flow_control.vhd",
# "ep_timestamping_unit.vhd",
# "ep_rmon_counters.vhd",
# "ep_rx_buffer.vhd",
"ep_rx_buffer.vhd",
"ep_sync_detect.vhd",
"ep_sync_detect_16bit.vhd",
"ep_wishbone_controller.vhd",
# "ep_ts_counter.vhd",
# "wrsw_endpoint.vhd",
"ep_registers_pkg.vhd",
"wr_fabric_pkg.vhd",
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 71f67994
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-10-18
-- Last update: 2011-10-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......
modules/wr_endpoint/ep_packet_filter.vhd
View file @ 71f67994
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-10-18
-- Last update: 2011-10-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......
modules/wr_endpoint/ep_rx_wb_master.vhd
View file @ 71f67994
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2011-10-18
-- Last update: 2011-10-24
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -64,7 +64,7 @@ begin -- behavioral
p_count_acks : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
if rst_n_i = '0' or src_out_int.cyc = '0' then
ack_count <= (others => '0');
else
if(src_out_int.stb = '1' and src_wb_i.stall = '0' and src_wb_i.ack = '0') then
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ 71f67994
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2011-10-05
-- Last update: 2011-10-18
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -44,16 +44,17 @@ use work.wr_fabric_pkg.all;
entity wr_endpoint is
generic (
g_simulation : boolean := true;
g_interface_mode : string := "SERDES";
g_rx_buffer_size_log2 : integer := 12;
g_simulation : boolean := false;
g_pcs_16bit : boolean := false;
g_rx_buffer_size : integer := 1024;
g_with_rx_buffer : boolean := true;
g_with_flow_control : boolean := true;
g_with_timestamper : boolean := true;
g_with_dmtd : boolean := true;
g_with_dpi_classifier : boolean := true;
g_with_vlans : boolean := true;
g_with_rtu : boolean := true
g_with_rtu : boolean := true;
g_with_leds : boolean := true
);
port (
......@@ -77,26 +78,43 @@ entity wr_endpoint is
pps_csync_p1_i : in std_logic;
-------------------------------------------------------------------------------
-- Xilinx GTP PHY Interace
-- PHY Interace (8/16 bit PCS)
-------------------------------------------------------------------------------
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
phy_prbsen_o : out std_logic;
phy_enable_o : out std_logic;
phy_syncen_o : out std_logic;
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_data_o : out std_logic_vector(15 downto 0);
phy_tx_k_o : out std_logic_vector(1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_data_i : in std_logic_vector(15 downto 0);
phy_rx_clk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_k_i : in std_logic_vector(1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rx_bitslide_i : in std_logic_vector(4 downto 0);
-------------------------------------------------------------------------------
-- GMII Interface (8-bit)
-------------------------------------------------------------------------------
gmii_tx_clk_i : in std_logic;
gmii_txd_o : out std_logic_vector(7 downto 0);
gmii_tx_en_o : out std_logic;
gmii_tx_er_o : out std_logic;
gmii_rx_clk_i : in std_logic;
gmii_rxd_i : in std_logic_vector(7 downto 0);
gmii_rx_er_i : in std_logic;
gmii_rx_dv_i : in std_logic;
---------------------------------------------------------------------------
-- Wishbone I/O
---------------------------------------------------------------------------
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
......@@ -178,7 +196,14 @@ entity wr_endpoint is
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic
wb_ack_o : out std_logic;
-------------------------------------------------------------------------------
-- Misc stuff
-------------------------------------------------------------------------------
led_link_o: out std_logic;
led_act_o: out std_logic
);
......@@ -215,7 +240,9 @@ architecture syn of wr_endpoint is
generic (
g_with_vlans : boolean;
g_with_dpi_classifier : boolean;
g_with_rtu : boolean);
g_with_rtu : boolean;
g_with_rx_buffer : boolean;
g_rx_buffer_size : integer);
port (
clk_sys_i : in std_logic;
clk_rx_i : in std_logic;
......@@ -224,9 +251,6 @@ architecture syn of wr_endpoint is
pcs_fab_i : in t_ep_internal_fabric;
pcs_fifo_almostfull_o : out std_logic;
pcs_busy_i : in std_logic;
oob_data_i : in std_logic_vector(47 downto 0);
oob_valid_i : in std_logic;
oob_ack_o : out std_logic;
src_wb_o : out t_wrf_source_out;
src_wb_i : in t_wrf_source_in;
fc_pause_p_o : out std_logic;
......@@ -240,9 +264,10 @@ architecture syn of wr_endpoint is
end component;
component ep_1000basex_pcs_8bit
component ep_1000basex_pcs
generic (
g_simulation : boolean);
g_simulation : boolean;
g_16bit : boolean);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -261,25 +286,24 @@ architecture syn of wr_endpoint is
serdes_rst_o : out std_logic;
serdes_syncen_o : out std_logic;
serdes_loopen_o : out std_logic;
serdes_prbsen_o : out std_logic;
serdes_enable_o : out std_logic;
serdes_tx_clk_i : in std_logic;
serdes_tx_data_o : out std_logic_vector(7 downto 0);
serdes_tx_k_o : out std_logic;
serdes_tx_data_o : out std_logic_vector(15 downto 0);
serdes_tx_k_o : out std_logic_vector(1 downto 0);
serdes_tx_disparity_i : in std_logic;
serdes_tx_enc_err_i : in std_logic;
serdes_rx_data_i : in std_logic_vector(7 downto 0);
serdes_rx_clk_i : in std_logic;
serdes_rx_k_i : in std_logic;
serdes_rx_data_i : in std_logic_vector(15 downto 0);
serdes_rx_k_i : in std_logic_vector(1 downto 0);
serdes_rx_enc_err_i : in std_logic;
serdes_rx_bitslide_i : in std_logic_vector(3 downto 0);
serdes_rx_bitslide_i : in std_logic_vector(4 downto 0);
rmon_o : inout t_rmon_triggers;
mdio_addr_i : in std_logic_vector(15 downto 0);
mdio_data_i : in std_logic_vector(15 downto 0);
mdio_data_o : out std_logic_vector(15 downto 0);
mdio_stb_i : in std_logic;
mdio_rw_i : in std_logic;
mdio_ready_o : out std_logic);
mdio_ready_o : out std_logic);
end component;
component ep_timestamping_unit
......@@ -325,10 +349,6 @@ architecture syn of wr_endpoint is
signal txoob_fid_value : std_logic_vector(15 downto 0);
signal txoob_fid_stb : std_logic;
signal rxoob_data : std_logic_vector(47 downto 0);
signal rxoob_valid : std_logic;
signal rxoob_ack : std_logic;
signal txpcs_timestamp_stb_p : std_logic;
signal rxpcs_timestamp_stb_p : std_logic;
signal rxpcs_timestamp_valid : std_logic;
......@@ -448,9 +468,10 @@ begin
mdio_addr <= regs_fromwb.mdio_asr_phyad_o & regs_fromwb.mdio_cr_addr_o;
U_PCS_1000BASEX : ep_1000basex_pcs_8bit
U_PCS_1000BASEX : ep_1000basex_pcs
generic map (
g_simulation => g_simulation)
g_simulation => g_simulation,
g_16bit => g_pcs_16bit)
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
......@@ -472,7 +493,6 @@ begin
serdes_rst_o => phy_rst_o,
serdes_loopen_o => phy_loopen_o,
serdes_prbsen_o => phy_prbsen_o,
serdes_enable_o => phy_enable_o,
serdes_syncen_o => phy_syncen_o,
......@@ -485,7 +505,7 @@ begin
serdes_rx_clk_i => phy_rx_clk_i,
serdes_rx_k_i => phy_rx_k_i,
serdes_rx_enc_err_i => phy_rx_enc_err_i,
serdes_rx_bitslide_i => phy_rx_bitslide_i,
serdes_rx_bitslide_i => phy_rx_bitslide_i(4 downto 0),
rmon_o => rmon,
......@@ -549,7 +569,9 @@ begin
generic map (
g_with_vlans => g_with_vlans,
g_with_dpi_classifier => g_with_dpi_classifier,
g_with_rtu => g_with_rtu)
g_with_rtu => g_with_rtu,
g_with_rx_buffer => g_with_rx_buffer,
g_rx_buffer_size => g_rx_buffer_size)
port map (
clk_sys_i => clk_sys_i,
clk_rx_i => phy_rx_clk_i,
......@@ -561,10 +583,6 @@ begin
pcs_fifo_almostfull_o => rxpcs_fifo_almostfull,
pcs_busy_i => rxpcs_busy,
oob_data_i => rxoob_data,
oob_valid_i => rxoob_valid,
oob_ack_o => rxoob_ack,
fc_pause_p_o => rxfra_pause_p,
fc_pause_delay_o => rxfra_pause_delay,
......
modules/wr_mini_nic/mini_nic.wb
View file @ 71f67994
......@@ -59,11 +59,22 @@ peripheral {
name = "RX DMA enable";
prefix = "RX_EN";
description = "1: RX buffer is allocated and initialized by the host, the miNIC can receive packets\n0: RX buffer not ready, reception is disabled";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "RX Accepted Packet Classes";
prefix = "RX_CLASS";
size = 8;
align = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX DMA Address";
......@@ -116,27 +127,26 @@ peripheral {
};
};
fifo_reg {
name = "TX timestamp FIFO";
prefix = "TSFIFO";
reg {
name = "TX timestamp register 0";
prefix = "TSR0";
size = 16;
direction = CORE_TO_BUS;
flags_bus = {FIFO_EMPTY};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "Timestamp value";
prefix = "TSVAL";
size = 32;
type = SLV;
};
field {
name = "Timestamp valid";
prefix = "VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Port ID";
prefix = "PID";
size = 5;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
......@@ -144,9 +154,29 @@ prefix = "TSVAL";
prefix = "FID";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "TX timestamp register 1";
prefix = "TSR1";
field {
name = "Timestamp value";
prefix = "TSVAL";
ack_read = "tx_ts_read_ack_o";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Debug register";
prefix = "DBGR";
......
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ 71f67994
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modules/wr_mini_nic/wr_mini_nic.vhd
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modules/wr_mini_nic/wr_mini_nic_wrfv2.vhd deleted 100644 → 0
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modules/wr_mini_nic/wr_minic_ep_combo.vhd deleted 100644 → 0
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modules/wr_mini_nic/wr_minic_ep_combo_with_rtu.vhd deleted 100644 → 0
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modules/wr_tbi_phy/Manifest.py
View file @ 71f67994
files = [ "dec_8b10b.vhd",
"enc_8b10b.vhd",
"wr_tbi_phy.vhd" ];
"enc_8b10b.vhd",
"wr_tbi_phy.vhd",
"disparity_gen_pkg.vhd" ];
platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd
View file @ 71f67994
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-15
-- Last update: 2011-10-17
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -50,6 +50,8 @@ use unisim.all;
library work;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gtp_phy_spartan6 is
......@@ -251,7 +253,7 @@ architecture rtl of wr_gtp_phy_spartan6 is
component gtp_bitslide
generic(
g_simulation : integer;
g_target : string := "spartan6");
g_target : string := "spartan6");
port (
gtp_rst_i : in std_logic;
gtp_rx_clk_i : in std_logic;
......@@ -338,8 +340,8 @@ architecture rtl of wr_gtp_phy_spartan6 is
signal ch0_rx_bitslide_int : std_logic_vector(4 downto 0);
signal ch1_rx_bitslide_int : std_logic_vector(4 downto 0);
component enc_8b10b
port (
clk_i : in std_logic;
......@@ -351,35 +353,50 @@ architecture rtl of wr_gtp_phy_spartan6 is
out_10b_o : out std_logic_vector(9 downto 0));
end component;
signal ch0_rst_n : std_logic;
signal ch1_rst_n : std_logic;
signal ch0_rst_n : std_logic;
signal ch1_rst_n : std_logic;
signal ch0_cur_disp : t_8b10b_disparity;
signal ch0_disp_pipe : std_logic_vector(1 downto 0);
signal ch1_cur_disp : t_8b10b_disparity;
signal ch1_disp_pipe : std_logic_vector(1 downto 0);
begin -- rtl
ch0_rst_n <= not ch0_gtp_reset;
ch1_rst_n <= not ch1_gtp_reset;
U_disp_gen: enc_8b10b
port map (
clk_i => ch0_ref_clk,
rst_n_i => ch0_rst_n,
ctrl_i => ch0_tx_k_i,
in_8b_i => ch0_tx_data_i,
err_o => open,
dispar_o => ch0_tx_disparity_o,
out_10b_o => open);
U_disp_gen2: enc_8b10b
port map (
clk_i => ch1_ref_clk,
rst_n_i => ch1_rst_n,
ctrl_i => ch1_tx_k_i,
in_8b_i => ch1_tx_data_i,
err_o => open,
dispar_o => ch1_tx_disparity_o,
out_10b_o => open);
gen_disp_ch0 : process(ch0_ref_clk)
begin
if rising_edge(ch0_ref_clk) then
if(ch0_rst_n = '0') then
ch0_cur_disp <= RD_MINUS;
ch0_disp_pipe <= (others => '0');
else
ch0_cur_disp <= f_next_8b10b_disparity8(ch0_cur_disp, ch0_tx_k_i, ch0_tx_data_i);
ch0_disp_pipe(0) <= to_std_logic(ch0_cur_disp);
ch0_disp_pipe(1) <= ch0_disp_pipe(0);
end if;
end if;
end process;
gen_disp_ch1 : process(ch1_ref_clk)
begin
if rising_edge(ch1_ref_clk) then
if(ch1_rst_n = '0') then
ch1_cur_disp <= RD_MINUS;
ch1_disp_pipe <= (others => '0');
else
ch1_cur_disp <= f_next_8b10b_disparity8(ch1_cur_disp, ch1_tx_k_i, ch1_tx_data_i);
ch1_disp_pipe(0) <= to_std_logic(ch1_cur_disp);
ch1_disp_pipe(1) <= ch1_disp_pipe(0);
end if;
end if;
end process;
ch0_tx_disparity_o <= ch0_disp_pipe(0);
ch1_tx_disparity_o <= ch1_disp_pipe(1);
p_gen_reset_ch0 : process(ch0_ref_clk)
begin
if rising_edge(ch0_ref_clk) then
......@@ -431,7 +448,7 @@ begin -- rtl
SERDESSTROBE => open,
I => ch0_gtp_clkout_int(0));
refbufg_ch0: BUFG
refbufg_ch0 : BUFG
port map (
I => ch0_ref_clk_out_buf,
O => ch0_ref_clk);
......@@ -446,13 +463,13 @@ begin -- rtl
SERDESSTROBE => open,
I => ch1_gtp_clkout_int(0));
refbufg_ch1: BUFG
refbufg_ch1 : BUFG
port map (
I => ch1_ref_clk_out_buf,
O => ch1_ref_clk);
end generate gen2;
gen3 : if(not g_ch0_use_refclk_out) generate
ch0_ref_clk <= ch0_ref_clk_i;
......@@ -601,6 +618,7 @@ begin -- rtl
align_en_i => ch0_gtp_locked,
align_done_o => ch0_align_done);
U_align_ch1 : gtp_phase_align
generic map (
g_simulation => g_simulation)
......@@ -645,7 +663,7 @@ begin -- rtl
ch1_rx_bitslide_o <= ch1_rx_bitslide_int(3 downto 0);
ch0_rx_enable_output <= ch0_rx_synced and ch0_align_done;
ch1_rx_enable_output <= ch1_rx_synced and ch1_align_done;
......@@ -717,10 +735,10 @@ begin -- rtl
-- drive the recovered clock output
ch0_rx_rbclk_o <= ch0_rx_rec_clk;
ch0_rx_rbclk_o <= ch0_rx_rec_clk;
-- ch0_tx_disparity_o <= ch0_tx_rundisp_vec(0);
ch1_rx_rbclk_o <= ch1_rx_rec_clk;
ch1_rx_rbclk_o <= ch1_rx_rec_clk;
-- ch1_tx_disparity_o <= ch1_tx_rundisp_vec(0);
ch0_ref_clk_o <= ch0_ref_clk;
......
platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd
View file @ 71f67994
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-13
-- Last update: 2011-10-17
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -49,6 +49,7 @@ use unisim.all;
library work;
use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gtx_phy_virtex6 is
......@@ -145,6 +146,7 @@ architecture rtl of wr_gtx_phy_virtex6 is
TXDATA_IN : in std_logic_vector(15 downto 0);
TXOUTCLK_OUT : out std_logic;
TXUSRCLK2_IN : in std_logic;
TXRUNDISP_OUT : out std_logic_vector(1 downto 0);
TXN_OUT : out std_logic;
TXP_OUT : out std_logic;
TXDLYALIGNDISABLE_IN : in std_logic;
......@@ -246,10 +248,17 @@ architecture rtl of wr_gtx_phy_virtex6 is
signal rx_data_int : std_logic_vector(15 downto 0);
signal rx_disp_err, rx_code_err : std_logic_vector(1 downto 0);
signal tx_is_k_swapped : std_logic_vector(1 downto 0);
signal tx_data_swapped : std_logic_vector(15 downto 0);
signal cur_disp : t_8b10b_disparity;
signal tx_rundisp_v6 : std_logic_vector(1 downto 0);
begin -- rtl
tx_enc_err_o <= '0';
p_gen_reset : process(clk_ref_i)
begin
......@@ -292,6 +301,9 @@ begin -- rtl
rx_rbclk_o <= rx_rec_clk;
tx_clk_o <= tx_out_clk;
tx_is_k_swapped <= tx_k_i(0) & tx_k_i(1);
tx_data_swapped <= tx_data_i(7 downto 0) & tx_data_i(15 downto 8);
U_GTX_INST : WHITERABBITGTX_WRAPPER_GTX
generic map (
GTX_SIM_GTXRESET_SPEEDUP => 1,
......@@ -316,13 +328,14 @@ begin -- rtl
PLLRXRESET_IN => '0',
RXPLLLKDET_OUT => rxpll_lockdet,
RXRESETDONE_OUT => rx_rst_done,
TXCHARISK_IN => tx_k_i,
TXCHARISK_IN => tx_is_k_swapped,
GTXTEST_IN => gtx_test,
TXDATA_IN => tx_data_i,
TXDATA_IN => tx_data_swapped,
TXOUTCLK_OUT => tx_out_clk_bufin,
TXUSRCLK2_IN => tx_out_clk,
TXN_OUT => pad_txp_o,
TXP_OUT => pad_txn_o,
TXRUNDISP_OUT => tx_rundisp_v6,
TXN_OUT => pad_txn_o,
TXP_OUT => pad_txp_o,
TXDLYALIGNDISABLE_IN => tx_dly_align_disable,
TXDLYALIGNMONENB_IN => '1',
TXDLYALIGNMONITOR_OUT => open,
......@@ -379,15 +392,27 @@ begin -- rtl
rx_enc_err_o <= '0';
elsif rising_edge(rx_rec_clk) then
if(everything_ready = '1' and rx_synced = '1') then
rx_data_o <= rx_data_int;
rx_k_o <= rx_k_int;
rx_data_o <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
rx_k_o <= rx_k_int(0) & rx_k_int(1);
rx_enc_err_o <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
else
rx_data_o <= (others => '1');
rx_k_o <= (others => '1');
rx_data_o <= (others => '1');
rx_k_o <= (others => '1');
rx_enc_err_o <= '1';
end if;
end if;
end if;
end process;
p_gen_tx_disparity : process(tx_out_clk)
begin
if rising_edge(tx_out_clk) then
if gtx_rst = '1' then
cur_disp <= RD_MINUS;
else
cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
end if;
end if;
end process;
tx_disparity_o <= to_std_logic(cur_disp);
end rtl;
sim/endpoint_mdio.v
View file @ 71f67994
......@@ -128,4 +128,4 @@
`define MDIO_WR_SPEC_CAL_CRST_OFFSET 2
`define MDIO_WR_SPEC_CAL_CRST 32'h00000004
`define MDIO_WR_SPEC_BSLIDE_OFFSET 4
`define MDIO_WR_SPEC_BSLIDE 32'h000000f0
`define MDIO_WR_SPEC_BSLIDE 32'h000001f0
sim/endpoint_regs.v
View file @ 71f67994
......@@ -77,32 +77,22 @@
`define EP_FCR_TX_QUANTA 32'hffff0000
`define ADDR_EP_MACH 8'h24
`define ADDR_EP_MACL 8'h28
`define ADDR_EP_DMCR 8'h2c
`define EP_DMCR_EN_OFFSET 0
`define EP_DMCR_EN 32'h00000001
`define EP_DMCR_N_AVG_OFFSET 16
`define EP_DMCR_N_AVG 32'h0fff0000
`define ADDR_EP_DMSR 8'h30
`define EP_DMSR_PS_VAL_OFFSET 0
`define EP_DMSR_PS_VAL 32'h00ffffff
`define EP_DMSR_PS_RDY_OFFSET 24
`define EP_DMSR_PS_RDY 32'h01000000
`define ADDR_EP_MDIO_CR 8'h34
`define ADDR_EP_MDIO_CR 8'h2c
`define EP_MDIO_CR_DATA_OFFSET 0
`define EP_MDIO_CR_DATA 32'h0000ffff
`define EP_MDIO_CR_ADDR_OFFSET 16
`define EP_MDIO_CR_ADDR 32'h00ff0000
`define EP_MDIO_CR_RW_OFFSET 31
`define EP_MDIO_CR_RW 32'h80000000
`define ADDR_EP_MDIO_ASR 8'h38
`define ADDR_EP_MDIO_ASR 8'h30
`define EP_MDIO_ASR_RDATA_OFFSET 0
`define EP_MDIO_ASR_RDATA 32'h0000ffff
`define EP_MDIO_ASR_PHYAD_OFFSET 16
`define EP_MDIO_ASR_PHYAD 32'h00ff0000
`define EP_MDIO_ASR_READY_OFFSET 31
`define EP_MDIO_ASR_READY 32'h80000000
`define ADDR_EP_IDCODE 8'h3c
`define ADDR_EP_DSR 8'h40
`define ADDR_EP_IDCODE 8'h34
`define ADDR_EP_DSR 8'h38
`define EP_DSR_LSTATUS_OFFSET 0
`define EP_DSR_LSTATUS 32'h00000001
`define EP_DSR_LACT_OFFSET 1
......
sim/if_wb_slave.svh
View file @ 71f67994
......@@ -58,8 +58,9 @@ interface IWishboneSlave
struct {
wb_cycle_type_t mode;
int gen_random_stalls;
int stall_min_duration;
int stall_max_duration;
real stall_prob;
} settings;
......@@ -107,10 +108,24 @@ interface IWishboneSlave
task gen_random_stalls();
if(settings.gen_random_stalls && probability_hit(settings.stall_prob))
stall <= 1;
else
stall <= 0;
static int stall_remaining = 0;
static int seed = 0;
// $display("stallr: %d\n", stall_remaining);
if(settings.gen_random_stalls && (probability_hit(settings.stall_prob) || stall_remaining > 0))
begin
if(stall_remaining == 0)
stall_remaining = $dist_uniform(seed,
settings.stall_min_duration,
settings.stall_max_duration);
if(stall_remaining)
stall_remaining--;
stall <= 1;
end else
stall <= 0;
endtask // gen_random_stalls
......
sim/simdrv_defs.svh
View file @ 71f67994
......@@ -2,6 +2,8 @@
`define SIMDRV_DEFS_SV 1
typedef longint unsigned uint64_t;
typedef shortint unsigned uint16_t;
typedef uint64_t u64_array_t[];
typedef byte byte_array_t[];
......
sim/wb_packet_sink.svh
View file @ 71f67994
......@@ -30,7 +30,7 @@ class WBPacketSink extends EthPacketSink;
endfunction // poll
protected task decode_status(uint64_t stat, ref EthPacket pkt);
if(stat & 'h2)
if(stat & 'h2)
pkt.error = 1'b1;
else begin
pkt.has_smac = (stat & 'h4 ? 1'b1 : 1'b0);
......@@ -38,14 +38,23 @@ class WBPacketSink extends EthPacketSink;
end
endtask // decode_status
protected task decode_oob(uint64_t oob, ref EthPacket pkt);
$display("DecodeOOB: %x", oob);
endtask // decode_oob
task recv(ref EthPacket pkt, ref int result = _null);
uint64_t oob = 0;
byte tmp[];
wb_cycle_t cyc;
int i, size = 0, n = 0;
int i, size = 0, n = 0, n_oob = 0;
bit with_oob = 0;
pkt = new;
pkt = new;
m_acc.get(cyc);
......@@ -79,9 +88,19 @@ class WBPacketSink extends EthPacketSink;
tmp[n++] = (xf.d & 'hff);
end
end
WRF_OOB:
begin
oob = (oob << 16) | xf.d;
with_oob = 1;
end
endcase // case (xf.a)
end
pkt.deserialize(tmp);
if(with_oob)
decode_oob(oob, pkt);
endtask // recv
......
testbench/wr_endpoint/full_tb/main.sv
View file @ 71f67994
This diff is collapsed.
testbench/wr_endpoint/full_tb/run.do
View file @ 71f67994
make -f Makefile
vsim -L unisim -t 10fs work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
run 80us
radix -hexadecimal
wave zoomfull
\ No newline at end of file
run 250us
wave zoomfull
radix -hexadecimal
testbench/wr_endpoint/full_tb/wave.do
View file @ 71f67994
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/clk_sys_i
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/rst_n_i
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/snk_fab_i
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/snk_dreq_o
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/src_fab_o
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/src_dreq_i
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/done_o
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/pclass_o
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/drop_o
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/regs_b
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/pc
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/ir
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/insn
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/done_int
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/regs
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/result_cmp
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/mask
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/ra
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/rb
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/rc
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/result1
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/result2
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/rd
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/pmem_addr
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/pmem_rdata
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/mm_addr
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/mm_write
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/mm_rdata
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/mm_wdata
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/stage1
add wave -noupdate /main/DUT/U_Rx_Deframer/gen_with_packet_filter/U_packet_filter/stage2
add wave -noupdate /main/clk_sys
add wave -noupdate /main/clk_ref
add wave -noupdate /main/clk_tdc
add wave -noupdate /main/rst_n
add wave -noupdate /main/trig_a
add wave -noupdate /main/trig_cal
add wave -noupdate /main/acam_wr_n
add wave -noupdate /main/acam_cs_n
add wave -noupdate /main/acam_rd_n
add wave -noupdate /main/acam_oe_n
add wave -noupdate /main/acam_adr
add wave -noupdate /main/acam_data
add wave -noupdate /main/tdc_d_o
add wave -noupdate /main/tdc_d_oe
add wave -noupdate /main/acam_start_dis
add wave -noupdate /main/acam_stop_dis
add wave -noupdate /main/acam_alutrigger
add wave -noupdate /main/trig_a_n_delayed
add wave -noupdate /main/tdc_start_delayed
add wave -noupdate /main/wr_utc
add wave -noupdate /main/wr_coarse
add wave -noupdate /main/wr_time_valid
add wave -noupdate /main/tdc_start_div
add wave -noupdate /main/tdc_start
add wave -noupdate /main/wr_time_valid_d0
add wave -noupdate /main/acam_ef1
add wave -noupdate /main/delay_len
add wave -noupdate /main/delay_pulse
add wave -noupdate /main/delay_val
add wave -noupdate /main/d_out
add wave -noupdate /main/spi_loop
add wave -noupdate /main/c_coarse_range
add wave -noupdate /main/fd_drv
add wave -noupdate /main/wb
add wave -noupdate /main/prev
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {14267727040 fs} 0}
configure wave -namecolwidth 150
WaveRestoreCursors {{Cursor 1} {20442364860 fs} 0}
configure wave -namecolwidth 413
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -47,4 +51,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {84 us}
WaveRestoreZoom {0 fs} {6754054050 fs}
testbench/wr_endpoint/old_ep/old_wrsw_endpoint.vhd
View file @ 71f67994
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Last update: 2011-05-11
-- Last update: 2011-10-17
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -572,7 +572,7 @@ begin
-- TX FRAMER
-------------------------------------------------------------------------------
txfra_enable <= link_ok and ep_ecr_tx_en_fra;
txfra_enable <= ep_ecr_tx_en_fra;
U_TX_FRA : old_ep_tx_framer
port map (
......
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