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White Rabbit core collection
Commit 70ddf23d authored by Peter Jansweijer's avatar Peter Jansweijer
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add generic g_dac_bits (default 16)

parent 43882eef
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    board/common/wr_board_pkg.vhd
    View file @ 70ddf23d
    ......@@ -123,6 +123,7 @@ package wr_board_pkg is
    g_diag_ver : integer := 0;
    g_diag_ro_size : integer := 0;
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16;
    g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
    g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
    g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
    ......@@ -141,9 +142,9 @@ package wr_board_pkg is
    pps_ext_i : in std_logic := '0';
    rst_n_i : in std_logic;
    dac_hpll_load_p1_o : out std_logic;
    dac_hpll_data_o : out std_logic_vector(15 downto 0);
    dac_hpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dpll_load_p1_o : out std_logic;
    dac_dpll_data_o : out std_logic_vector(15 downto 0);
    dac_dpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    phy8_o : out t_phy_8bits_from_wrc;
    phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
    phy16_o : out t_phy_16bits_from_wrc;
    ......@@ -196,7 +197,7 @@ package wr_board_pkg is
    wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
    aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
    tm_dac_value_o : out std_logic_vector(23 downto 0);
    tm_dac_value_o : out std_logic_vector(31 downto 0);
    tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
    tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
    ......
    board/common/xwrc_board_common.vhd
    View file @ 70ddf23d
    ......@@ -73,6 +73,7 @@ entity xwrc_board_common is
    g_diag_ver : integer := 0;
    g_diag_ro_size : integer := 0;
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16;
    g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
    g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
    g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
    ......@@ -113,10 +114,10 @@ entity xwrc_board_common is
    --Timing system
    ---------------------------------------------------------------------------
    dac_hpll_load_p1_o : out std_logic;
    dac_hpll_data_o : out std_logic_vector(15 downto 0);
    dac_hpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dpll_load_p1_o : out std_logic;
    dac_dpll_data_o : out std_logic_vector(15 downto 0);
    dac_dpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    ---------------------------------------------------------------------------
    -- PHY I/f
    ......@@ -220,7 +221,7 @@ entity xwrc_board_common is
    ---------------------------------------------------------------------------
    -- Aux clocks control
    ---------------------------------------------------------------------------
    tm_dac_value_o : out std_logic_vector(23 downto 0);
    tm_dac_value_o : out std_logic_vector(31 downto 0);
    tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
    tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
    ......@@ -396,7 +397,8 @@ begin -- architecture struct
    g_diag_id => c_diag_id,
    g_diag_ver => c_diag_ver,
    g_diag_ro_size => c_diag_ro_size,
    g_diag_rw_size => c_diag_rw_size)
    g_diag_rw_size => c_diag_rw_size,
    g_dac_bits => g_dac_bits)
    port map (
    clk_sys_i => clk_sys_i,
    clk_dmtd_i => clk_dmtd_i,
    ......
    modules/wr_sit5359_interface/wr_sit5359_interface.vhd
    View file @ 70ddf23d
    ......@@ -51,9 +51,10 @@ use work.sit5359_wbgen2_pkg.all;
    entity wr_sit5359_interface is
    generic (
    g_simulation : integer := 0;
    g_simulation : integer := 0;
    g_sys_clock_freq : integer := 62500000;
    g_i2c_freq : integer := 400000
    g_i2c_freq : integer := 400000;
    g_dac_bits : integer range 1 to 26 := 16 -- SiTime 5359 Frequency Control word = 26 bits
    );
    port (
    ......@@ -61,7 +62,7 @@ entity wr_sit5359_interface is
    rst_n_i : in std_logic;
    -- WR Core timing interface: aux clock tune port
    tm_dac_value_i : in std_logic_vector(15 downto 0) := (others => '0');
    tm_dac_value_i : in std_logic_vector(g_dac_bits-1 downto 0) := (others => '0');
    tm_dac_value_wr_i : in std_logic := '0';
    -- I2C bus: output enable (active low)
    ......@@ -106,15 +107,17 @@ architecture rtl of wr_sit5359_interface is
    regs_o : out t_sit5359_out_registers);
    end component;
    constant c_dac_half_scale : integer := 2**(g_dac_bits-1);
    signal regs_in : t_sit5359_in_registers;
    signal regs_out : t_sit5359_out_registers;
    signal rfreq_new_p : std_logic;
    signal rfreq_current, rfreq_new : unsigned(31 downto 0);
    signal tm_dac_value_wr_d : std_logic;
    signal tm_dac_value_wr_d : std_logic;
    signal tm_dac_value_wr_d1 : std_logic;
    signal tm_dac_value : std_logic_vector(15 downto 0);
    signal tm_dac_value : std_logic_vector(g_dac_bits-1 downto 0);
    signal i2c_tick : std_logic;
    signal i2c_divider : unsigned(7 downto 0);
    ......@@ -244,9 +247,9 @@ begin -- rtl
    -- next pipeline stage, create fromatted frequency tune word
    if(tm_dac_value_wr_d = '1' and tm_dac_value_wr_d1 = '0') then
    -- Sit5359 Freqency Control Word is 26 bits signed
    -- Convert 16 bit unsigned DAC value to 17 bit signed and
    -- shift DAC bits to MSB bits of 26 bit Freqency Control Word.
    rfreq_new <= "00000" & regs_out.cr_osc_oe_o & unsigned((signed('0' & tm_dac_value(15 downto 0)) - to_signed(32768, 17)) & "000000000");
    -- Convert "g_dac_bits" unsigned DAC value to signed and shift left DAC bits and pad with '0'
    -- to compose 26 bit Freqency Control Word (including Output Enable bit).
    rfreq_new <= "00000" & regs_out.cr_osc_oe_o & unsigned(signed(tm_dac_value) - to_signed(c_dac_half_scale, g_dac_bits)) & ((25-g_dac_bits) downto 0 => '0');
    end if;
    rfreq_new_p <= tm_dac_value_wr_d and not tm_dac_value_wr_d1 and regs_out.cr_spll_en_o;
    ......
    modules/wr_sit5359_interface/xwr_sit5359_interface.vhd
    View file @ 70ddf23d
    ......@@ -40,12 +40,13 @@ use work.wishbone_pkg.all;
    entity xwr_sit5359_interface is
    generic (
    g_simulation : integer := 0);
    g_simulation : integer := 0;
    g_dac_bits : integer := 16);
    port (
    clk_sys_i : in std_logic;
    rst_n_i : in std_logic;
    tm_dac_value_i : in std_logic_vector(15 downto 0) := (others => '0');
    tm_dac_value_i : in std_logic_vector(g_dac_bits-1 downto 0) := (others => '0');
    tm_dac_value_wr_i : in std_logic := '0';
    scl_pad_oen_o : out std_logic;
    ......@@ -62,11 +63,12 @@ architecture wrapper of xwr_sit5359_interface is
    component wr_sit5359_interface
    generic (
    g_simulation : integer);
    g_simulation : integer;
    g_dac_bits : integer);
    port (
    clk_sys_i : in std_logic;
    rst_n_i : in std_logic;
    tm_dac_value_i : in std_logic_vector(15 downto 0) := (others => '0');
    tm_dac_value_i : in std_logic_vector(g_dac_bits-1 downto 0) := (others => '0');
    tm_dac_value_wr_i : in std_logic := '0';
    scl_pad_oen_o : out std_logic;
    sda_pad_oen_o : out std_logic;
    ......@@ -88,7 +90,8 @@ begin -- wrapper
    U_Wrapped_sit5359 : wr_sit5359_interface
    generic map (
    g_simulation => g_simulation)
    g_simulation => g_simulation,
    g_dac_bits => g_dac_bits)
    port map (
    clk_sys_i => clk_sys_i,
    rst_n_i => rst_n_i,
    ......
    modules/wr_softpll_ng/wr_softpll_ng.vhd
    View file @ 70ddf23d
    ......@@ -6,7 +6,7 @@
    -- Author : Tomasz Włostowski
    -- Company : CERN BE-CO-HT
    -- Created : 2011-01-29
    -- Last update: 2019-09-18
    -- Last update: 2022-01-28
    -- Platform : FPGA-generic
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    ......@@ -56,6 +56,7 @@ entity wr_softpll_ng is
    -- should be log2(N) + 7 == 21. Note: the value must match the TAG_BITS constant
    -- in spll_defs.h file!
    g_tag_bits : integer;
    g_dac_bits : integer := 16;
    -- These two are obvious:
    g_num_ref_inputs : integer := 1;
    ......@@ -127,12 +128,12 @@ entity wr_softpll_ng is
    pps_ext_a_i : in std_logic;
    -- DMTD oscillator drive
    dac_dmtd_data_o : out std_logic_vector(15 downto 0);
    dac_dmtd_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    -- When HI, load the data from dac_dmtd_data_o to the DAC.
    dac_dmtd_load_o : out std_logic;
    -- Output channel DAC value
    dac_out_data_o : out std_logic_vector(15 downto 0);
    dac_out_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    -- Output channel select (0 = Output channel 0, 1 == OC 1, etc...)
    dac_out_sel_o : out std_logic_vector(3 downto 0);
    dac_out_load_o : out std_logic;
    ......
    modules/wr_softpll_ng/xwr_softpll_ng.vhd
    View file @ 70ddf23d
    ......@@ -6,7 +6,7 @@
    -- Author : Tomasz Włostowski
    -- Company : CERN BE-CO-HT
    -- Created : 2011-01-29
    -- Last update: 2018-11-07
    -- Last update: 2022-01-28
    -- Platform : FPGA-generic
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    ......@@ -51,6 +51,7 @@ entity xwr_softpll_ng is
    -- should be log2(N) + 7 == 21. Note: the value must match the TAG_BITS constant
    -- in spll_defs.h file!
    g_tag_bits : integer;
    g_dac_bits : integer := 16;
    -- These two are obvious:
    g_num_ref_inputs : integer := 1;
    ......@@ -117,11 +118,11 @@ entity xwr_softpll_ng is
    pps_ext_a_i : in std_logic;
    -- DMTD oscillator drive
    dac_dmtd_data_o : out std_logic_vector(15 downto 0);
    dac_dmtd_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dmtd_load_o : out std_logic;
    -- Output channel DAC value
    dac_out_data_o : out std_logic_vector(15 downto 0);
    dac_out_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    -- Output channel select (0 = channel 0, etc. )
    dac_out_sel_o : out std_logic_vector(3 downto 0);
    dac_out_load_o : out std_logic;
    ......@@ -144,6 +145,7 @@ architecture wrapper of xwr_softpll_ng is
    component wr_softpll_ng
    generic (
    g_tag_bits : integer;
    g_dac_bits : integer;
    g_num_ref_inputs : integer;
    g_num_outputs : integer;
    g_num_exts : integer;
    ......@@ -172,9 +174,9 @@ architecture wrapper of xwr_softpll_ng is
    clk_ext_rst_o : out std_logic;
    pps_csync_p1_i : in std_logic;
    pps_ext_a_i : in std_logic;
    dac_dmtd_data_o : out std_logic_vector(15 downto 0);
    dac_dmtd_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dmtd_load_o : out std_logic;
    dac_out_data_o : out std_logic_vector(15 downto 0);
    dac_out_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_out_sel_o : out std_logic_vector(3 downto 0);
    dac_out_load_o : out std_logic;
    out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
    ......@@ -199,6 +201,7 @@ begin -- behavioral
    U_Wrapped_Softpll : wr_softpll_ng
    generic map (
    g_tag_bits => g_tag_bits,
    g_dac_bits => g_dac_bits,
    g_interface_mode => g_interface_mode,
    g_address_granularity => g_address_granularity,
    g_num_ref_inputs => g_num_ref_inputs,
    ......
    modules/wrc_core/wr_core.vhd
    View file @ 70ddf23d
    ......@@ -6,7 +6,7 @@
    -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
    -- Company : CERN (BE-CO-HT)
    -- Created : 2011-02-02
    -- Last update: 2022-03-28
    -- Last update: 2022-04-19
    -- Platform : FPGA-generics
    -- Standard : VHDL
    -------------------------------------------------------------------------------
    ......@@ -104,8 +104,8 @@ entity wr_core is
    g_diag_id : integer := 0;
    g_diag_ver : integer := 0;
    g_diag_ro_size : integer := 0;
    g_diag_rw_size : integer := 0
    );
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16);
    port(
    ---------------------------------------------------------------------------
    -- Clocks/resets
    ......@@ -140,10 +140,10 @@ entity wr_core is
    --Timing system
    -----------------------------------------
    dac_hpll_load_p1_o : out std_logic;
    dac_hpll_data_o : out std_logic_vector(15 downto 0);
    dac_hpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dpll_load_p1_o : out std_logic;
    dac_dpll_data_o : out std_logic_vector(15 downto 0);
    dac_dpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    -- PHY I/f
    phy_ref_clk_i : in std_logic;
    ......@@ -293,7 +293,7 @@ entity wr_core is
    tm_link_up_o : out std_logic;
    -- DAC Control
    tm_dac_value_o : out std_logic_vector(23 downto 0);
    tm_dac_value_o : out std_logic_vector(31 downto 0);
    tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
    -- Aux clock lock enable
    tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    ......@@ -518,7 +518,7 @@ architecture struct of wr_core is
    signal spll_out_locked : std_logic_vector(g_aux_clks downto 0);
    signal dac_dpll_data : std_logic_vector(15 downto 0);
    signal dac_dpll_data : std_logic_vector(g_dac_bits-1 downto 0);
    signal dac_dpll_sel : std_logic_vector(3 downto 0);
    signal dac_dpll_load_p1 : std_logic;
    ......@@ -647,6 +647,7 @@ begin
    g_divide_input_by_2 => not g_pcs_16bit,
    g_with_debug_fifo => g_softpll_enable_debugger,
    g_tag_bits => 22,
    g_dac_bits => g_dac_bits,
    g_interface_mode => PIPELINED,
    g_address_granularity => BYTE,
    g_num_ref_inputs => 1,
    ......@@ -708,7 +709,7 @@ begin
    dac_dpll_data_o <= dac_dpll_data;
    dac_dpll_load_p1_o <= '1' when (dac_dpll_load_p1 = '1' and dac_dpll_sel = x"0") else '0';
    tm_dac_value_o <= x"00" & dac_dpll_data;
    tm_dac_value_o <= (31 downto dac_dpll_data'length => '0') & dac_dpll_data;
    p_decode_dac_writes : process(dac_dpll_load_p1, dac_dpll_sel)
    begin
    ......
    modules/wrc_core/wrcore_pkg.vhd
    View file @ 70ddf23d
    ......@@ -6,7 +6,7 @@
    -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
    -- Company : CERN (BE-CO-HT)
    -- Created : 2011-05-11
    -- Last update: 2022-03-28
    -- Last update: 2022-04-19
    -- Platform : FPGA-generics
    -- Standard : VHDL
    -------------------------------------------------------------------------------
    ......@@ -331,6 +331,7 @@ package wrcore_pkg is
    component xwr_softpll_ng
    generic (
    g_tag_bits : integer;
    g_dac_bits : integer;
    g_num_ref_inputs : integer;
    g_num_outputs : integer;
    g_num_exts : integer;
    ......@@ -359,9 +360,9 @@ package wrcore_pkg is
    clk_ext_rst_o : out std_logic;
    pps_csync_p1_i : in std_logic;
    pps_ext_a_i : in std_logic;
    dac_dmtd_data_o : out std_logic_vector(15 downto 0);
    dac_dmtd_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dmtd_load_o : out std_logic;
    dac_out_data_o : out std_logic_vector(15 downto 0);
    dac_out_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_out_sel_o : out std_logic_vector(3 downto 0);
    dac_out_load_o : out std_logic;
    out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
    ......@@ -411,7 +412,8 @@ package wrcore_pkg is
    g_diag_id : integer := 0;
    g_diag_ver : integer := 0;
    g_diag_ro_size : integer := 0;
    g_diag_rw_size : integer := 0);
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16);
    port(
    clk_sys_i : in std_logic;
    clk_dmtd_i : in std_logic := '0';
    ......@@ -426,9 +428,9 @@ package wrcore_pkg is
    rst_n_i : in std_logic;
    dac_hpll_load_p1_o : out std_logic;
    dac_hpll_data_o : out std_logic_vector(15 downto 0);
    dac_hpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dpll_load_p1_o : out std_logic;
    dac_dpll_data_o : out std_logic_vector(15 downto 0);
    dac_dpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    -----------------------------------------
    -- PHY I/f
    -----------------------------------------
    ......@@ -511,7 +513,7 @@ package wrcore_pkg is
    fc_tx_pause_ready_o : out std_logic;
    tm_link_up_o : out std_logic;
    tm_dac_value_o : out std_logic_vector(23 downto 0);
    tm_dac_value_o : out std_logic_vector(31 downto 0);
    tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
    tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
    ......@@ -566,7 +568,8 @@ package wrcore_pkg is
    g_diag_id : integer := 0;
    g_diag_ver : integer := 0;
    g_diag_ro_size : integer := 0;
    g_diag_rw_size : integer := 0);
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16);
    port(
    ---------------------------------------------------------------------------
    -- Clocks/resets
    ......@@ -601,10 +604,10 @@ package wrcore_pkg is
    --Timing system
    -----------------------------------------
    dac_hpll_load_p1_o : out std_logic;
    dac_hpll_data_o : out std_logic_vector(15 downto 0);
    dac_hpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dpll_load_p1_o : out std_logic;
    dac_dpll_data_o : out std_logic_vector(15 downto 0);
    dac_dpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    -----------------------------------------
    -- PHY I/f
    ......@@ -758,7 +761,7 @@ package wrcore_pkg is
    tm_link_up_o : out std_logic;
    tm_dac_value_o : out std_logic_vector(23 downto 0);
    tm_dac_value_o : out std_logic_vector(31 downto 0);
    tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0) ;
    tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0) ;
    ......
    modules/wrc_core/xwr_core.vhd
    View file @ 70ddf23d
    ......@@ -6,7 +6,7 @@
    -- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
    -- Company : CERN (BE-CO-HT)
    -- Created : 2011-02-02
    -- Last update: 2022-01-17
    -- Last update: 2022-04-19
    -- Platform : FPGA-generics
    -- Standard : VHDL
    -------------------------------------------------------------------------------
    ......@@ -104,8 +104,8 @@ entity xwr_core is
    g_diag_id : integer := 0;
    g_diag_ver : integer := 0;
    g_diag_ro_size : integer := 0;
    g_diag_rw_size : integer := 0
    );
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16);
    port(
    ---------------------------------------------------------------------------
    -- Clocks/resets
    ......@@ -140,10 +140,10 @@ entity xwr_core is
    --Timing system
    -----------------------------------------
    dac_hpll_load_p1_o : out std_logic;
    dac_hpll_data_o : out std_logic_vector(15 downto 0);
    dac_hpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    dac_dpll_load_p1_o : out std_logic;
    dac_dpll_data_o : out std_logic_vector(15 downto 0);
    dac_dpll_data_o : out std_logic_vector(g_dac_bits-1 downto 0);
    -----------------------------------------
    -- PHY I/f
    ......@@ -258,7 +258,7 @@ entity xwr_core is
    tm_link_up_o : out std_logic;
    -- DAC Control
    tm_dac_value_o : out std_logic_vector(23 downto 0);
    tm_dac_value_o : out std_logic_vector(31 downto 0);
    tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
    -- Aux clock lock enable
    tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    ......@@ -317,6 +317,7 @@ begin
    g_diag_ver => g_diag_ver,
    g_diag_ro_size => g_diag_ro_size,
    g_diag_rw_size => g_diag_rw_size,
    g_dac_bits => g_dac_bits,
    g_use_platform_specific_dpram => g_use_platform_specific_dpram
    )
    port map(
    ......
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