platform: add GTX wrapper for Xilinx Kintex 7

7069cf95 · Peter Jansweijer · Grzegorz Daniluk · a8edc000 · 7069cf95 · 7069cf95
Commit 7069cf95 authored Jan 08, 2014 by Peter Jansweijer Committed by Grzegorz Daniluk Jan 13, 2015
4 changed files
--- a/platform/xilinx/wr_gtp_phy/Manifest.py
+++ b/platform/xilinx/wr_gtp_phy/Manifest.py
-files = ["gtp_bitslide.vhd",
-				 "gtp_phase_align.vhd",
-				 "gtp_phase_align_virtex6.vhd",
-				 "gtx_reset.vhd",
-				 "whiterabbitgtx_wrapper_gtx.vhd",
-#				 "whiterabbitgtp_wrapper.vhd",
-				 "whiterabbitgtp_wrapper_tile.vhd",
-				 "wr_gtp_phy_spartan6.vhd",
-				 "wr_gtx_phy_virtex6.vhd"];
+files = [ "gtp_bitslide.vhd",
+          "gtp_phase_align.vhd",
+          "gtp_phase_align_virtex6.vhd",
+          "gtx_reset.vhd",
+          "whiterabbitgtx_wrapper_gtx.vhd",
+#         "whiterabbitgtp_wrapper.vhd",
+          "whiterabbitgtp_wrapper_tile.vhd",
+          "whiterabbit_gtxe2_channel_wrapper_gt.vhd",
+          "wr_gtp_phy_spartan6.vhd",
+          "wr_gtx_phy_virtex6.vhd",
+          "wr_gtx_phy_kintex7.vhd"];
--- a/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
--- a/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
+++ b/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd
--- a/platform/xilinx/wr_xilinx_pkg.vhd
+++ b/platform/xilinx/wr_xilinx_pkg.vhd
@@ -50,4 +50,28 @@ package wr_xilinx_pkg is
      pad_rxp1_i         : in  std_logic                    := '0');
  end component;

+  component wr_gtx_phy_kintex7 is
+    generic (
+      -- set to non-zero value to speed up the simulation by reducing some delays
+      g_simulation : integer := 0);
+    port (
+      clk_gtx_i      : in  std_logic;
+      tx_out_clk_o   : out std_logic;
+      tx_data_i      : in  std_logic_vector(15 downto 0);
+      tx_k_i         : in  std_logic_vector(1 downto 0);
+      tx_disparity_o : out std_logic;
+      tx_enc_err_o   : out std_logic;
+      rx_rbclk_o     : out std_logic;
+      rx_data_o      : out std_logic_vector(15 downto 0);
+      rx_k_o         : out std_logic_vector(1 downto 0);
+      rx_enc_err_o   : out std_logic;
+      rx_bitslide_o  : out std_logic_vector(4 downto 0);
+      rst_i          : in  std_logic;
+      loopen_i       : in  std_logic;
+      pad_txn_o      : out std_logic;
+      pad_txp_o      : out std_logic;
+      pad_rxn_i      : in  std_logic := '0';
+      pad_rxp_i      : in  std_logic := '0');
+  end component;
+
 end wr_xilinx_pkg;