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6fd625d4
Commit
6fd625d4
authored
Aug 06, 2018
by
Tomasz Wlostowski
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Plain Diff
xwrc_board_spec: added DDR controller clock output with programmable divider
parent
9a218b52
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4 changed files
with
34 additions
and
7 deletions
+34
-7
wr_spec_pkg.vhd
board/spec/wr_spec_pkg.vhd
+4
-2
xwrc_board_spec.vhd
board/spec/xwrc_board_spec.vhd
+12
-3
wr_xilinx_pkg.vhd
platform/xilinx/wr_xilinx_pkg.vhd
+4
-1
xwrc_platform_xilinx.vhd
platform/xilinx/xwrc_platform_xilinx.vhd
+14
-1
No files found.
board/spec/wr_spec_pkg.vhd
View file @
6fd625d4
...
@@ -7,7 +7,7 @@
...
@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Created : 2017-02-17
-- Last update: 2018-0
3-20
-- Last update: 2018-0
7-25
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-- Copyright (c) 2017 CERN
...
@@ -58,7 +58,8 @@ package wr_spec_pkg is
...
@@ -58,7 +58,8 @@ package wr_spec_pkg is
g_diag_id
:
integer
:
=
0
;
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_size
:
integer
:
=
0
;
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
);
g_diag_rw_size
:
integer
:
=
0
;
g_ddr_clock_divider
:
integer
:
=
3
);
port
(
port
(
areset_n_i
:
in
std_logic
;
areset_n_i
:
in
std_logic
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
...
@@ -74,6 +75,7 @@ package wr_spec_pkg is
...
@@ -74,6 +75,7 @@ package wr_spec_pkg is
clk_ref_125m_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
clk_ddr_o
:
out
std_logic
;
plldac_sclk_o
:
out
std_logic
;
plldac_sclk_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
plldac_din_o
:
out
std_logic
;
pll25dac_cs_n_o
:
out
std_logic
;
pll25dac_cs_n_o
:
out
std_logic
;
...
...
board/spec/xwrc_board_spec.vhd
View file @
6fd625d4
...
@@ -7,7 +7,7 @@
...
@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Created : 2017-02-17
-- Last update: 2018-07-
04
-- Last update: 2018-07-
25
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- Description: Top-level wrapper for WR PTP core including all the modules
...
@@ -76,7 +76,10 @@ entity xwrc_board_spec is
...
@@ -76,7 +76,10 @@ entity xwrc_board_spec is
g_diag_ver
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
-- size the generic diag interface
-- size the generic diag interface
g_diag_ro_size
:
integer
:
=
0
;
g_diag_ro_size
:
integer
:
=
0
;
g_diag_rw_size
:
integer
:
=
0
g_diag_rw_size
:
integer
:
=
0
;
-- DDR clock divider setting
g_ddr_clock_divider
:
integer
:
=
3
);
);
port
(
port
(
---------------------------------------------------------------------------
---------------------------------------------------------------------------
...
@@ -103,6 +106,8 @@ entity xwrc_board_spec is
...
@@ -103,6 +106,8 @@ entity xwrc_board_spec is
clk_sys_62m5_o
:
out
std_logic
;
clk_sys_62m5_o
:
out
std_logic
;
-- 125MHz ref clock output
-- 125MHz ref clock output
clk_ref_125m_o
:
out
std_logic
;
clk_ref_125m_o
:
out
std_logic
;
-- Programmable frequency DDR controller clock output (divider set in g_ddr3_clock_divider)
clk_ddr_o
:
out
std_logic
;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o
:
out
std_logic
;
rst_sys_62m5_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
...
@@ -268,6 +273,7 @@ architecture struct of xwrc_board_spec is
...
@@ -268,6 +273,7 @@ architecture struct of xwrc_board_spec is
-- PLLs, clocks
-- PLLs, clocks
signal
clk_pll_62m5
:
std_logic
;
signal
clk_pll_62m5
:
std_logic
;
signal
clk_pll_125m
:
std_logic
;
signal
clk_pll_125m
:
std_logic
;
signal
clk_pll_ddr
:
std_logic
;
signal
clk_pll_dmtd
:
std_logic
;
signal
clk_pll_dmtd
:
std_logic
;
signal
pll_locked
:
std_logic
;
signal
pll_locked
:
std_logic
;
signal
clk_10m_ext
:
std_logic
;
signal
clk_10m_ext
:
std_logic
;
...
@@ -320,7 +326,8 @@ begin -- architecture struct
...
@@ -320,7 +326,8 @@ begin -- architecture struct
g_fpga_family
=>
"spartan6"
,
g_fpga_family
=>
"spartan6"
,
g_with_external_clock_input
=>
g_with_external_clock_input
,
g_with_external_clock_input
=>
g_with_external_clock_input
,
g_use_default_plls
=>
TRUE
,
g_use_default_plls
=>
TRUE
,
g_simulation
=>
g_simulation
)
g_simulation
=>
g_simulation
,
g_ddr_clock_divider
=>
g_ddr_clock_divider
)
port
map
(
port
map
(
areset_n_i
=>
areset_n_i
,
areset_n_i
=>
areset_n_i
,
clk_10m_ext_i
=>
clk_10m_ext_i
,
clk_10m_ext_i
=>
clk_10m_ext_i
,
...
@@ -338,6 +345,7 @@ begin -- architecture struct
...
@@ -338,6 +345,7 @@ begin -- architecture struct
clk_62m5_sys_o
=>
clk_pll_62m5
,
clk_62m5_sys_o
=>
clk_pll_62m5
,
clk_125m_ref_o
=>
clk_pll_125m
,
clk_125m_ref_o
=>
clk_pll_125m
,
clk_62m5_dmtd_o
=>
clk_pll_dmtd
,
clk_62m5_dmtd_o
=>
clk_pll_dmtd
,
clk_ddr_o
=>
clk_pll_ddr
,
pll_locked_o
=>
pll_locked
,
pll_locked_o
=>
pll_locked
,
clk_10m_ext_o
=>
clk_10m_ext
,
clk_10m_ext_o
=>
clk_10m_ext
,
phy8_o
=>
phy8_to_wrc
,
phy8_o
=>
phy8_to_wrc
,
...
@@ -349,6 +357,7 @@ begin -- architecture struct
...
@@ -349,6 +357,7 @@ begin -- architecture struct
clk_sys_62m5_o
<=
clk_pll_62m5
;
clk_sys_62m5_o
<=
clk_pll_62m5
;
clk_ref_125m_o
<=
clk_pll_125m
;
clk_ref_125m_o
<=
clk_pll_125m
;
clk_ddr_o
<=
clk_pll_ddr
;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Reset logic
-- Reset logic
...
...
platform/xilinx/wr_xilinx_pkg.vhd
View file @
6fd625d4
...
@@ -45,7 +45,9 @@ package wr_xilinx_pkg is
...
@@ -45,7 +45,9 @@ package wr_xilinx_pkg is
g_use_default_plls
:
boolean
:
=
TRUE
;
g_use_default_plls
:
boolean
:
=
TRUE
;
g_gtp_enable_ch0
:
integer
:
=
0
;
g_gtp_enable_ch0
:
integer
:
=
0
;
g_gtp_enable_ch1
:
integer
:
=
1
;
g_gtp_enable_ch1
:
integer
:
=
1
;
g_simulation
:
integer
:
=
0
);
g_simulation
:
integer
:
=
0
;
g_ddr_clock_divider
:
integer
:
=
3
);
port
(
port
(
areset_n_i
:
in
std_logic
:
=
'1'
;
areset_n_i
:
in
std_logic
:
=
'1'
;
clk_10m_ext_i
:
in
std_logic
:
=
'0'
;
clk_10m_ext_i
:
in
std_logic
:
=
'0'
;
...
@@ -64,6 +66,7 @@ package wr_xilinx_pkg is
...
@@ -64,6 +66,7 @@ package wr_xilinx_pkg is
clk_ext_locked_i
:
in
std_logic
:
=
'1'
;
clk_ext_locked_i
:
in
std_logic
:
=
'1'
;
clk_ext_stopped_i
:
in
std_logic
:
=
'0'
;
clk_ext_stopped_i
:
in
std_logic
:
=
'0'
;
clk_ext_rst_o
:
out
std_logic
;
clk_ext_rst_o
:
out
std_logic
;
clk_ddr_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_txp_o
:
out
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
...
...
platform/xilinx/xwrc_platform_xilinx.vhd
View file @
6fd625d4
...
@@ -64,7 +64,8 @@ entity xwrc_platform_xilinx is
...
@@ -64,7 +64,8 @@ entity xwrc_platform_xilinx is
g_gtp_enable_ch0
:
integer
:
=
0
;
g_gtp_enable_ch0
:
integer
:
=
0
;
g_gtp_enable_ch1
:
integer
:
=
1
;
g_gtp_enable_ch1
:
integer
:
=
1
;
-- Set to TRUE will speed up some initialization processes
-- Set to TRUE will speed up some initialization processes
g_simulation
:
integer
:
=
0
g_simulation
:
integer
:
=
0
;
g_ddr_clock_divider
:
integer
:
=
3
);
);
port
(
port
(
---------------------------------------------------------------------------
---------------------------------------------------------------------------
...
@@ -125,6 +126,7 @@ entity xwrc_platform_xilinx is
...
@@ -125,6 +126,7 @@ entity xwrc_platform_xilinx is
clk_125m_ref_o
:
out
std_logic
;
clk_125m_ref_o
:
out
std_logic
;
clk_ref_locked_o
:
out
std_logic
;
clk_ref_locked_o
:
out
std_logic
;
clk_62m5_dmtd_o
:
out
std_logic
;
clk_62m5_dmtd_o
:
out
std_logic
;
clk_ddr_o
:
out
std_logic
;
pll_locked_o
:
out
std_logic
;
pll_locked_o
:
out
std_logic
;
clk_10m_ext_o
:
out
std_logic
;
clk_10m_ext_o
:
out
std_logic
;
-- PHY
-- PHY
...
@@ -196,6 +198,7 @@ begin -- architecture rtl
...
@@ -196,6 +198,7 @@ begin -- architecture rtl
signal
clk_dmtd_fb
:
std_logic
;
signal
clk_dmtd_fb
:
std_logic
;
signal
pll_dmtd_locked
:
std_logic
;
signal
pll_dmtd_locked
:
std_logic
;
signal
clk_20m_vcxo_buf
:
std_logic
;
signal
clk_20m_vcxo_buf
:
std_logic
;
signal
clk_ddr
:
std_logic
;
begin
--gen_spartan6_default_plls
begin
--gen_spartan6_default_plls
...
@@ -211,11 +214,15 @@ begin -- architecture rtl
...
@@ -211,11 +214,15 @@ begin -- architecture rtl
CLKOUT0_DIVIDE
=>
16
,
CLKOUT0_DIVIDE
=>
16
,
CLKOUT0_PHASE
=>
0
.
000
,
CLKOUT0_PHASE
=>
0
.
000
,
CLKOUT0_DUTY_CYCLE
=>
0
.
500
,
CLKOUT0_DUTY_CYCLE
=>
0
.
500
,
CLKOUT1_DIVIDE
=>
3
,
CLKOUT1_PHASE
=>
0
.
000
,
CLKOUT1_DUTY_CYCLE
=>
0
.
500
,
CLKIN_PERIOD
=>
8
.
0
,
CLKIN_PERIOD
=>
8
.
0
,
REF_JITTER
=>
0
.
016
)
REF_JITTER
=>
0
.
016
)
port
map
(
port
map
(
CLKFBOUT
=>
clk_sys_fb
,
CLKFBOUT
=>
clk_sys_fb
,
CLKOUT0
=>
clk_sys
,
CLKOUT0
=>
clk_sys
,
CLKOUT1
=>
clk_ddr
,
LOCKED
=>
pll_sys_locked
,
LOCKED
=>
pll_sys_locked
,
RST
=>
pll_arst
,
RST
=>
pll_arst
,
CLKFBIN
=>
clk_sys_fb
,
CLKFBIN
=>
clk_sys_fb
,
...
@@ -227,6 +234,12 @@ begin -- architecture rtl
...
@@ -227,6 +234,12 @@ begin -- architecture rtl
O
=>
clk_125m_pllref_buf
,
O
=>
clk_125m_pllref_buf
,
I
=>
clk_125m_pllref_i
);
I
=>
clk_125m_pllref_i
);
-- DDR PLL global clock buffer
cmp_ddr_clk_buf_o
:
BUFG
port
map
(
O
=>
clk_ddr_o
,
I
=>
clk_ddr
);
-- System PLL output clock buffer
-- System PLL output clock buffer
cmp_clk_sys_buf_o
:
BUFG
cmp_clk_sys_buf_o
:
BUFG
port
map
(
port
map
(
...
...
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