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White Rabbit core collection
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White Rabbit core collection
Commits
6c434a4c
Commit
6c434a4c
authored
Mar 10, 2021
by
Javier D. Garcia-Lasheras
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Plain Diff
Support the DDR3 at PL as an XDMA AXI high-bandwidth peripheral for test purposes
parent
0c446e81
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4 changed files
with
330 additions
and
17 deletions
+330
-17
wr_spec7_pkg.vhd
board/spec7/wr_spec7_pkg.vhd
+15
-0
processing_system_pcie.tcl
platform/xilinx/wr_pcie/processing_system_pcie.tcl
+242
-15
spec7_wr_ref_top.vhd
top/spec7_ref_design/spec7_wr_ref_top.vhd
+37
-1
spec7_write_top.vhd
top/spec7_write_design/spec7_write_top.vhd
+36
-1
No files found.
board/spec7/wr_spec7_pkg.vhd
View file @
6c434a4c
...
...
@@ -225,6 +225,21 @@ package wr_spec7_pkg is
DDR_dq
:
inout
STD_LOGIC_VECTOR
(
31
downto
0
);
DDR_dqs_n
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR_dqs_p
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR3_dq
:
inout
STD_LOGIC_VECTOR
(
31
downto
0
);
DDR3_dqs_p
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR3_dqs_n
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR3_addr
:
out
STD_LOGIC_VECTOR
(
14
downto
0
);
DDR3_ba
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
DDR3_ras_n
:
out
STD_LOGIC
;
DDR3_cas_n
:
out
STD_LOGIC
;
DDR3_we_n
:
out
STD_LOGIC
;
DDR3_reset_n
:
out
STD_LOGIC
;
DDR3_ck_p
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_ck_n
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_cke
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_cs_n
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_dm
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR3_odt
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
FIXED_IO_mio
:
inout
STD_LOGIC_VECTOR
(
53
downto
0
);
FIXED_IO_ddr_vrn
:
inout
STD_LOGIC
;
FIXED_IO_ddr_vrp
:
inout
STD_LOGIC
;
...
...
platform/xilinx/wr_pcie/processing_system_pcie.tcl
View file @
6c434a4c
This diff is collapsed.
Click to expand it.
top/spec7_ref_design/spec7_wr_ref_top.vhd
View file @
6c434a4c
...
...
@@ -246,7 +246,28 @@ entity spec7_wr_ref_top is
FIXED_IO_mio
:
inout
STD_LOGIC_VECTOR
(
53
downto
0
);
FIXED_IO_ps_clk
:
inout
STD_LOGIC
;
FIXED_IO_ps_porb
:
inout
STD_LOGIC
;
FIXED_IO_ps_srstb
:
inout
STD_LOGIC
FIXED_IO_ps_srstb
:
inout
STD_LOGIC
;
---------------------------------------------------------------------------
-- Programmable Logic DDR3
---------------------------------------------------------------------------
DDR3_dq
:
inout
STD_LOGIC_VECTOR
(
31
downto
0
);
DDR3_dqs_p
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR3_dqs_n
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR3_addr
:
out
STD_LOGIC_VECTOR
(
14
downto
0
);
DDR3_ba
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
DDR3_ras_n
:
out
STD_LOGIC
;
DDR3_cas_n
:
out
STD_LOGIC
;
DDR3_we_n
:
out
STD_LOGIC
;
DDR3_reset_n
:
out
STD_LOGIC
;
DDR3_ck_p
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_ck_n
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_cke
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_cs_n
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_dm
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR3_odt
:
out
STD_LOGIC_VECTOR
(
0
to
0
)
);
end
entity
spec7_wr_ref_top
;
...
...
@@ -349,6 +370,21 @@ begin -- architecture top
Pcie
:
processing_system_pcie_wrapper
port
map
(
DDR3_addr
=>
DDR3_addr
,
DDR3_ba
=>
DDR3_ba
,
DDR3_cas_n
=>
DDR3_cas_n
,
DDR3_ck_n
=>
DDR3_ck_n
,
DDR3_ck_p
=>
DDR3_ck_p
,
DDR3_cke
=>
DDR3_cke
,
DDR3_cs_n
=>
DDR3_cs_n
,
DDR3_dm
=>
DDR3_dm
,
DDR3_dq
=>
DDR3_dq
,
DDR3_dqs_n
=>
DDR3_dqs_n
,
DDR3_dqs_p
=>
DDR3_dqs_p
,
DDR3_odt
=>
DDR3_odt
,
DDR3_ras_n
=>
DDR3_ras_n
,
DDR3_reset_n
=>
DDR3_reset_n
,
DDR3_we_n
=>
DDR3_we_n
,
DDR_addr
=>
DDR_addr
,
DDR_ba
=>
DDR_ba
,
DDR_cas_n
=>
DDR_cas_n
,
...
...
top/spec7_write_design/spec7_write_top.vhd
View file @
6c434a4c
...
...
@@ -222,7 +222,27 @@ entity spec7_write_top is
FIXED_IO_mio
:
inout
STD_LOGIC_VECTOR
(
53
downto
0
);
FIXED_IO_ps_clk
:
inout
STD_LOGIC
;
FIXED_IO_ps_porb
:
inout
STD_LOGIC
;
FIXED_IO_ps_srstb
:
inout
STD_LOGIC
FIXED_IO_ps_srstb
:
inout
STD_LOGIC
;
---------------------------------------------------------------------------
-- Programmable Logic DDR3
---------------------------------------------------------------------------
DDR3_dq
:
inout
STD_LOGIC_VECTOR
(
31
downto
0
);
DDR3_dqs_p
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR3_dqs_n
:
inout
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR3_addr
:
out
STD_LOGIC_VECTOR
(
14
downto
0
);
DDR3_ba
:
out
STD_LOGIC_VECTOR
(
2
downto
0
);
DDR3_ras_n
:
out
STD_LOGIC
;
DDR3_cas_n
:
out
STD_LOGIC
;
DDR3_we_n
:
out
STD_LOGIC
;
DDR3_reset_n
:
out
STD_LOGIC
;
DDR3_ck_p
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_ck_n
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_cke
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_cs_n
:
out
STD_LOGIC_VECTOR
(
0
to
0
);
DDR3_dm
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
DDR3_odt
:
out
STD_LOGIC_VECTOR
(
0
to
0
)
);
end
entity
spec7_write_top
;
...
...
@@ -347,6 +367,21 @@ pci_clk_buf : IBUFDS_GTE2
);
Pcie
:
processing_system_pcie_wrapper
port
map
(
DDR3_addr
=>
DDR3_addr
,
DDR3_ba
=>
DDR3_ba
,
DDR3_cas_n
=>
DDR3_cas_n
,
DDR3_ck_n
=>
DDR3_ck_n
,
DDR3_ck_p
=>
DDR3_ck_p
,
DDR3_cke
=>
DDR3_cke
,
DDR3_cs_n
=>
DDR3_cs_n
,
DDR3_dm
=>
DDR3_dm
,
DDR3_dq
=>
DDR3_dq
,
DDR3_dqs_n
=>
DDR3_dqs_n
,
DDR3_dqs_p
=>
DDR3_dqs_p
,
DDR3_odt
=>
DDR3_odt
,
DDR3_ras_n
=>
DDR3_ras_n
,
DDR3_reset_n
=>
DDR3_reset_n
,
DDR3_we_n
=>
DDR3_we_n
,
DDR_addr
=>
DDR_addr
,
DDR_ba
=>
DDR_ba
,
DDR_cas_n
=>
DDR_cas_n
,
...
...
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