Skip to content

W
White Rabbit core collection
Commit 63edfdae authored by Peter Jansweijer's avatar Peter Jansweijer
Browse files
Options

Updated spec7_ref_design for AD9516 125->215 initialisation

parent b2a37277
Hide whitespace changes
Inline Side-by-side
Showing with 68 additions and 4 deletions
top/spec7_ref_design/spec7_wr_ref_top.vhd
View file @ 63edfdae
......@@ -93,6 +93,20 @@ entity spec7_wr_ref_top is
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
pll_refsel_o : out std_logic;
pll_lock_i : in std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
......@@ -130,6 +144,9 @@ entity spec7_wr_ref_top is
led_link_o : out std_logic;
reset_n_i : in std_logic;
suicide_n_o : out std_logic;
wdog_n_o : out std_logic;
prsnt_m2c_l_i : in std_logic;
------------------------------------------------------------------------------
-- Digital I/O Bulls-Eye connections
......@@ -266,6 +283,11 @@ architecture top of spec7_wr_ref_top is
begin -- architecture top
-- Never trigger PS_POR or PROGRAM_B
suicide_n_o <= '1';
wdog_n_o <= '1';
-- prsnt_m2c_l_i isn't used but must be defined as input.
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
......@@ -295,6 +317,16 @@ begin -- architecture top
dac_dmtd_sclk_o => dac_dmtd_sclk_o,
dac_dmtd_din_o => dac_dmtd_din_o,
pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
pll_refsel_o => pll_refsel_o,
pll_lock_i => pll_lock_i,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
......
top/spec7_ref_design/spec7_wr_ref_top.xdc
View file @ 63edfdae
......@@ -61,6 +61,29 @@ set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_sclk_o]
set_property PACKAGE_PIN D10 [get_ports dac_refclk_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_cs_n_o]
# -------------------------------------------------------------------------------
# -- AD9516 PLL Control signals
# -------------------------------------------------------------------------------
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN B11 [get_ports pll_status_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_status_i]
set_property PACKAGE_PIN B12 [get_ports pll_mosi_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_mosi_o]
set_property PACKAGE_PIN C11 [get_ports pll_miso_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_miso_i]
set_property PACKAGE_PIN A15 [get_ports pll_sck_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_sck_o]
set_property PACKAGE_PIN A14 [get_ports pll_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_cs_n_o]
set_property PACKAGE_PIN B14 [get_ports pll_sync_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_sync_n_o]
set_property PACKAGE_PIN C12 [get_ports pll_reset_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_reset_n_o]
set_property PACKAGE_PIN C14 [get_ports pll_refsel_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_refsel_o]
set_property PACKAGE_PIN A12 [get_ports pll_lock_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_lock_i]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
......@@ -123,8 +146,8 @@ set_property IOSTANDARD LVCMOS25 [get_ports led_link_o]
set_property PACKAGE_PIN AB25 [get_ports led_act_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_act_o]
# LED_0
#set_property PACKAGE_PIN AC26 [get_ports led_0]
#set_property IOSTANDARD LVCMOS25 [get_ports led_0]
#set_property PACKAGE_PIN AC26 [get_ports led_pps]
#set_property IOSTANDARD LVCMOS25 [get_ports led_pps]
# LED_1
#set_property PACKAGE_PIN AB26 [get_ports led_1]
#set_property IOSTANDARD LVCMOS25 [get_ports led_1]
......@@ -152,6 +175,15 @@ set_property IOSTANDARD LVCMOS25 [get_ports led_act_o]
set_property PACKAGE_PIN AA20 [get_ports reset_n_i]
set_property IOSTANDARD LVCMOS25 [get_ports reset_n_i]
# Suicide & Watchdog
# Bank 13 (HR) VCCO - 2.5 V
set_property PACKAGE_PIN AC22 [get_ports suicide_n_o]
set_property IOSTANDARD LVCMOS25 [get_ports suicide_n_o]
set_property PACKAGE_PIN AC21 [get_ports wdog_n_o]
set_property IOSTANDARD LVCMOS25 [get_ports wdog_n_o]
set_property PACKAGE_PIN V19 [get_ports prsnt_m2c_l_i]
set_property IOSTANDARD LVCMOS25 [get_ports prsnt_m2c_l_i]
# SI570
# Bank 12 (HR) VCCO - 2.5 V
#set_property PACKAGE_PIN AD14 [get_ports si570_clk_n]
......@@ -449,10 +481,10 @@ set_property IOSTANDARD LVCMOS25 [get_ports dio_led_bot_o]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 23
#set_property PACKAGE_PIN Y20 [get_ports fmc_la05_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la05_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 25
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 25
#set_property PACKAGE_PIN W18 [get_ports fmc_la06_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la06_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 27
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 27
#set_property PACKAGE_PIN W19 [get_ports fmc_la06_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la06_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 29
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment