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White Rabbit core collection
Commit 638600b4 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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Convert SDWB to the new SDB format.

parent cd879ba4
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Showing with 757 additions and 957 deletions
modules/wr_eca/xwr_eca_pkg.vhd
View file @ 638600b4
......@@ -6,20 +6,21 @@ use work.wishbone_pkg.all;
use work.gencores_pkg.all;
package xwr_eca_pkg is
constant c_xwr_eca_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"000000000000001f",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"04", -- 32-bit port granularity
constant c_xwr_eca_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"00000651", -- GSI
dev_device => x"8752bf44",
dev_version => x"00000001",
dev_date => x"20120319",
description => "GSI_ECA_UNIT ");
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001f",
product => (
vendor_id => x"0000000000000651",
device_id => x"8752bf44",
version => x"00000001",
date => x"20120319",
name => "GSI_ECA_UNIT ")));
component xwr_eca is
generic(
......
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 638600b4
......@@ -99,20 +99,21 @@ package endpoint_pkg is
led_act_o : out std_logic);
end component;
constant c_xwr_endpoint_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"00000000000000ff",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"07", -- 8/16/32-bit port granularity
constant c_xwr_endpoint_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"0000CE42", -- CERN
dev_device => x"650c2d4f",
dev_version => x"00000001",
dev_date => x"20120305",
description => "WR-Endpoint ");
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"650c2d4f",
version => x"00000001",
date => x"20120305",
name => "WR-Endpoint ")));
component xwr_endpoint
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
......
modules/wr_tlu/wb_cores_pkg_gsi.vhd
View file @ 638600b4
......@@ -8,20 +8,21 @@ use work.wishbone_pkg.all;
package wb_cores_pkg_gsi is
constant c_xwr_wb_timestamp_latch_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"00000000000007ff",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"04", -- 8/16/32-bit port granularity
constant c_xwr_wb_timestamp_latch_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"00000651", -- GSI
dev_device => x"10051981",
dev_version => x"00000001",
dev_date => x"20120308",
description => "GSI_TM_LATCH ");
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000007ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"10051981",
version => x"00000001",
date => x"20120308",
name => "GSI_TM_LATCH ")));
component fake_timestamp
port (
......
modules/wrc_core/wr_core.vhd
View file @ 638600b4
......@@ -27,7 +27,7 @@
-- Date Version Author Description
-- 2011-02-02 1.0 greg.d Created
-- 2011-10-25 2.0 greg.d Redesigned and wishbonized
-- 2012-03-05 3.0 wterpstra Added SDWB descriptors
-- 2012-03-05 3.0 wterpstra Added SDB descriptors
-------------------------------------------------------------------------------
......@@ -288,17 +288,17 @@ architecture struct of wr_core is
-----------------------------------------------------------------------------
--WB Secondary Crossbar
-----------------------------------------------------------------------------
constant c_secbar_layout : t_sdwb_device_array(6 downto 0) :=
(0 => f_sdwb_set_address(c_xwr_mini_nic_sdwb, x"00000000"),
1 => f_sdwb_set_address(c_xwr_endpoint_sdwb, x"00000100"),
2 => f_sdwb_set_address(c_xwr_softpll_ng_sdwb, x"00000200"),
3 => f_sdwb_set_address(c_xwr_pps_gen_sdwb, x"00000300"),
4 => f_sdwb_set_address(c_wrc_periph0_sdwb, x"00000400"), -- Syscon
5 => f_sdwb_set_address(c_wrc_periph1_sdwb, x"00000500"), -- UART
6 => f_sdwb_set_address(c_wrc_periph2_sdwb, x"00000600")); -- 1-Wire
constant c_secbar_sdwb_address : t_wishbone_address := x"00000800";
constant c_secbar_bridge_sdwb : t_sdwb_device :=
f_xwb_bridge_layout_sdwb(true, c_secbar_layout, c_secbar_sdwb_address);
constant c_secbar_layout : t_sdb_record_array(6 downto 0) :=
(0 => f_sdb_embed_device(c_xwr_mini_nic_sdb, x"00000000"),
1 => f_sdb_embed_device(c_xwr_endpoint_sdb, x"00000100"),
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00000200"),
3 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00000300"),
4 => f_sdb_embed_device(c_wrc_periph0_sdb, x"00000400"), -- Syscon
5 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000500"), -- UART
6 => f_sdb_embed_device(c_wrc_periph2_sdb, x"00000600")); -- 1-Wire
constant c_secbar_sdb_address : t_wishbone_address := x"00000800";
constant c_secbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_secbar_layout, c_secbar_sdb_address);
signal secbar_master_i : t_wishbone_master_in_array(6 downto 0);
signal secbar_master_o : t_wishbone_master_out_array(6 downto 0);
......@@ -306,10 +306,10 @@ architecture struct of wr_core is
-----------------------------------------------------------------------------
--WB intercon
-----------------------------------------------------------------------------
constant c_layout : t_sdwb_device_array(1 downto 0) :=
(0 => f_sdwb_set_address(f_xwb_dpram(g_dpram_size), x"00000000"),
1 => f_sdwb_set_address(c_secbar_bridge_sdwb, x"00020000"));
constant c_sdwb_address : t_wishbone_address := x"00030000";
constant c_layout : t_sdb_record_array(1 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(g_dpram_size), x"00000000"),
1 => f_sdb_embed_bridge(c_secbar_bridge_sdb, x"00020000"));
constant c_sdb_address : t_wishbone_address := x"00030000";
signal cbar_slave_i : t_wishbone_slave_in_array (2 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(2 downto 0);
......@@ -733,14 +733,14 @@ begin
-----------------------------------------------------------------------------
-- WB intercon
-----------------------------------------------------------------------------
WB_CON : xwb_sdwb_crossbar
WB_CON : xwb_sdb_crossbar
generic map(
g_num_masters => 3,
g_num_slaves => 2,
g_registered => true,
g_wraparound => true,
g_layout => c_layout,
g_sdwb_addr => c_sdwb_address
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys_i,
......@@ -802,14 +802,14 @@ begin
-----------------------------------------------------------------------------
-- WB Secondary Crossbar
-----------------------------------------------------------------------------
WB_SECONDARY_CON : xwb_sdwb_crossbar
WB_SECONDARY_CON : xwb_sdb_crossbar
generic map(
g_num_masters => 1,
g_num_slaves => 7,
g_registered => true,
g_wraparound => true,
g_layout => c_secbar_layout,
g_sdwb_addr => c_secbar_sdwb_address
g_sdb_addr => c_secbar_sdb_address
)
port map(
clk_sys_i => clk_sys_i,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 638600b4
......@@ -20,20 +20,21 @@ package wrcore_pkg is
-----------------------------------------------------------------------------
--PPS generator
-----------------------------------------------------------------------------
constant c_xwr_pps_gen_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"00000000000000ff",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"07", -- 8/16/32-bit port granularity
constant c_xwr_pps_gen_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"0000CE42", -- CERN
dev_device => x"de0d8ced",
dev_version => x"00000001",
dev_date => x"20120305",
description => "WR-PPS-Generator");
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"de0d8ced",
version => x"00000001",
date => x"20120305",
name => "WR-PPS-Generator ")));
component xwr_pps_gen is
generic(
g_interface_mode : t_wishbone_interface_mode;
......@@ -62,20 +63,21 @@ package wrcore_pkg is
-----------------------------------------------------------------------------
--Mini NIC
-----------------------------------------------------------------------------
constant c_xwr_mini_nic_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"00000000000000ff",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"07", -- 8/16/32-bit port granularity
constant c_xwr_mini_nic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"0000CE42", -- CERN
dev_device => x"ab28633a",
dev_version => x"00000001",
dev_date => x"20120305",
description => "WR-Mini-NIC ");
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"ab28633a",
version => x"00000001",
date => x"20120305",
name => "WR-Mini-NIC ")));
component xwr_mini_nic
generic (
g_interface_mode : t_wishbone_interface_mode;
......@@ -123,48 +125,51 @@ package wrcore_pkg is
);
end component;
constant c_wrc_periph0_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"00000000000000ff",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"07", -- 8/16/32-bit port granularity
constant c_wrc_periph0_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"0000CE42", -- CERN
dev_device => x"ff07fc47",
dev_version => x"00000001",
dev_date => x"20120305",
description => "WR-Periph-Syscon");
constant c_wrc_periph1_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"00000000000000ff",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"07", -- 8/16/32-bit port granularity
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"ff07fc47",
version => x"00000001",
date => x"20120305",
name => "WR-Periph-Syscon ")));
constant c_wrc_periph1_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"0000CE42", -- CERN
dev_device => x"e2d13d04",
dev_version => x"00000001",
dev_date => x"20120305",
description => "WR-Periph-UART ");
constant c_wrc_periph2_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"00000000000000ff",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"07", -- 8/16/32-bit port granularity
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"e2d13d04",
version => x"00000001",
date => x"20120305",
name => "WR-Periph-UART ")));
constant c_wrc_periph2_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"0000CE42", -- CERN
dev_device => x"779c5443",
dev_version => x"00000001",
dev_date => x"20120305",
description => "WR-Periph-1Wire ");
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"779c5443",
version => x"00000001",
date => x"20120305",
name => "WR-Periph-1Wire ")));
component wrc_periph is
generic(
g_phys_uart : boolean := true;
......@@ -203,21 +208,21 @@ package wrcore_pkg is
-----------------------------------------------------------------------------
-- Soft-PLL
-----------------------------------------------------------------------------
constant c_xwr_softpll_ng_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"00000000000000ff",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"07", -- 8/16/32-bit port granularity
constant c_xwr_softpll_ng_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"0000CE42", -- CERN
dev_device => x"65158dc0",
dev_version => x"00000001",
dev_date => x"20120305",
description => "WR-Soft-PLL ");
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"65158dc0",
version => x"00000001",
date => x"20120305",
name => "WR-Soft-PLL ")));
component xwr_softpll_ng
generic (
g_tag_bits : integer;
......
syn/gsi_exploder/wr_core_demo/exploder_top.qsf
View file @ 638600b4
......@@ -108,6 +108,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
set_global_assignment -name VHDL_FILE ../../../modules/wr_softpll_ng/wr_softpll_ng.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wr_softpll_ng/spll_wb_slave.vhd
......@@ -123,8 +125,6 @@ set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/w
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdwb_rom.vhd"
set_global_assignment -name VHDL_FILE "../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdwb_crossbar.vhd"
set_global_assignment -name SDC_FILE ../../../top/gsi_exploder/wr_core_demo/exploder_top.sdc
set_global_assignment -name VHDL_FILE ../../../top/gsi_exploder/wr_core_demo/spec_serial_dac_arb.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_exploder/wr_core_demo/spec_serial_dac.vhd
......
syn/gsi_scu/wr_core_demo/scu.qsf
View file @ 638600b4
This source diff could not be displayed because it is too large. You can view the blob instead.
top/gsi_exploder/wr_core_demo/exploder_top.vhd
View file @ 638600b4
......@@ -212,20 +212,21 @@ architecture rtl of exploder_top is
dac_din_o : out std_logic);
end component;
constant c_xwr_gpio_32_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"000000000000001f",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"04", -- 8/16/32-bit port granularity
constant c_xwr_gpio_32_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"00000651", -- GSI
dev_device => x"35aa6b95",
dev_version => x"00000001",
dev_date => x"20120305",
description => "GSI_GPIO_32 ");
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001f",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"35aa6b95",
version => x"00000001",
date => x"20120305",
name => "GSI_GPIO_32 ")));
component flash_loader
port (
......@@ -234,18 +235,18 @@ architecture rtl of exploder_top is
end component;
-- WR core layout
constant c_wrcore_bridge_sdwb : t_sdwb_device := f_xwb_bridge_manual_sdwb(x"0003ffff", x"00030000");
constant c_wrcore_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Ref clock crossbar
constant c_ref_slaves : natural := 3;
constant c_ref_masters : natural := 1;
constant c_ref_layout : t_sdwb_device_array(c_ref_slaves-1 downto 0) :=
(0 => f_sdwb_set_address(c_xwr_gpio_32_sdwb, x"00000000"),
1 => f_sdwb_set_address(c_xwr_eca_sdwb, x"00040000"),
2 => f_sdwb_set_address(c_xwr_wb_timestamp_latch_sdwb, x"00080000"));
constant c_ref_sdwb_address : t_wishbone_address := x"000C0000";
constant c_ref_bridge : t_sdwb_device :=
f_xwb_bridge_layout_sdwb(true, c_ref_layout, c_ref_sdwb_address);
constant c_ref_layout : t_sdb_record_array(c_ref_slaves-1 downto 0) :=
(0 => f_sdb_embed_device(c_xwr_gpio_32_sdb, x"00000000"),
1 => f_sdb_embed_device(c_xwr_eca_sdb, x"00040000"),
2 => f_sdb_embed_device(c_xwr_wb_timestamp_latch_sdb, x"00080000"));
constant c_ref_sdb_address : t_wishbone_address := x"000C0000";
constant c_ref_bridge : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_ref_layout, c_ref_sdb_address);
signal cbar_ref_slave_i : t_wishbone_slave_in_array (c_ref_masters-1 downto 0);
signal cbar_ref_slave_o : t_wishbone_slave_out_array(c_ref_masters-1 downto 0);
......@@ -256,11 +257,11 @@ architecture rtl of exploder_top is
constant c_slaves : natural := 3;
constant c_masters : natural := 1;
constant c_test_dpram_size : natural := 2048;
constant c_layout : t_sdwb_device_array(c_slaves-1 downto 0) :=
(0 => f_sdwb_set_address(f_xwb_dpram(c_test_dpram_size), x"00000000"),
1 => f_sdwb_set_address(c_ref_bridge, x"00100000"),
2 => f_sdwb_set_address(c_wrcore_bridge_sdwb, x"00200000"));
constant c_sdwb_address : t_wishbone_address := x"00300000";
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(c_test_dpram_size), x"00000000"),
1 => f_sdb_embed_bridge(c_ref_bridge, x"00100000"),
2 => f_sdb_embed_bridge(c_wrcore_bridge_sdb , x"00200000"));
constant c_sdb_address : t_wishbone_address := x"00300000";
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
......@@ -581,14 +582,14 @@ begin
mb_master_in.stall <= '0';
mb_master_in.dat <= std_logic_vector(to_unsigned(0,mb_master_in.dat'length-pio_reg'length)) & pio_reg;
GSI_REF_CON : xwb_sdwb_crossbar
GSI_REF_CON : xwb_sdb_crossbar
generic map(
g_num_masters => c_ref_masters,
g_num_slaves => c_ref_slaves,
g_registered => true,
g_wraparound => true,
g_layout => c_ref_layout,
g_sdwb_addr => c_ref_sdwb_address)
g_sdb_addr => c_ref_sdb_address)
port map(
clk_sys_i => clk_125m_pllref_p,
rst_n_i => nreset,
......@@ -609,14 +610,14 @@ begin
master_i => cbar_ref_slave_o(0),
master_o => cbar_ref_slave_i(0));
GSI_CON : xwb_sdwb_crossbar
GSI_CON : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true,
g_layout => c_layout,
g_sdwb_addr => c_sdwb_address)
g_sdb_addr => c_sdb_address)
port map(
clk_sys_i => l_clkp,
rst_n_i => nreset,
......
top/gsi_scu/wr_core_demo/scu_top.vhd
View file @ 638600b4
......@@ -307,20 +307,21 @@ architecture rtl of scu_top is
master_o : out t_wishbone_master_out);
end component;
constant c_xwr_gpio_32_sdwb : t_sdwb_device := (
wbd_begin => x"0000000000000000",
wbd_end => x"000000000000001f",
sdwb_child => x"0000000000000000",
wbd_flags => x"01", -- big-endian, no-child, present
wbd_width => x"04", -- 8/16/32-bit port granularity
constant c_xwr_gpio_32_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
abi_class => x"00000000", -- undocumented device
dev_vendor => x"00000651", -- GSI
dev_device => x"35aa6b95",
dev_version => x"00000001",
dev_date => x"20120305",
description => "GSI_GPIO_32 ");
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001f",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"35aa6b95",
version => x"00000001",
date => x"20120305",
name => "GSI_GPIO_32 ")));
component flash_loader
port (
......@@ -370,19 +371,19 @@ architecture rtl of scu_top is
);
end component lpc_uart;
-- WR core layout
constant c_wrcore_bridge_sdwb : t_sdwb_device := f_xwb_bridge_manual_sdwb(x"0003ffff", x"00030000");
-- WR core layout
constant c_wrcore_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
-- Ref clock crossbar
constant c_ref_slaves : natural := 3;
constant c_ref_masters : natural := 1;
constant c_ref_layout : t_sdwb_device_array(c_ref_slaves-1 downto 0) :=
(0 => f_sdwb_set_address(c_xwr_gpio_32_sdwb, x"00000000"),
1 => f_sdwb_set_address(c_xwr_eca_sdwb, x"00040000"),
2 => f_sdwb_set_address(c_xwr_wb_timestamp_latch_sdwb, x"00080000"));
constant c_ref_sdwb_address : t_wishbone_address := x"000C0000";
constant c_ref_bridge : t_sdwb_device :=
f_xwb_bridge_layout_sdwb(true, c_ref_layout, c_ref_sdwb_address);
constant c_ref_layout : t_sdb_record_array(c_ref_slaves-1 downto 0) :=
(0 => f_sdb_embed_device(c_xwr_gpio_32_sdb, x"00000000"),
1 => f_sdb_embed_device(c_xwr_eca_sdb, x"00040000"),
2 => f_sdb_embed_device(c_xwr_wb_timestamp_latch_sdb, x"00080000"));
constant c_ref_sdb_address : t_wishbone_address := x"000C0000";
constant c_ref_bridge : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_ref_layout, c_ref_sdb_address);
signal cbar_ref_slave_i : t_wishbone_slave_in_array (c_ref_masters-1 downto 0);
signal cbar_ref_slave_o : t_wishbone_slave_out_array(c_ref_masters-1 downto 0);
......@@ -393,11 +394,11 @@ architecture rtl of scu_top is
constant c_slaves : natural := 3;
constant c_masters : natural := 2;
constant c_test_dpram_size : natural := 2048;
constant c_layout : t_sdwb_device_array(c_slaves-1 downto 0) :=
(0 => f_sdwb_set_address(f_xwb_dpram(c_test_dpram_size), x"00000000"),
1 => f_sdwb_set_address(c_ref_bridge, x"00100000"),
2 => f_sdwb_set_address(c_wrcore_bridge_sdwb, x"00200000"));
constant c_sdwb_address : t_wishbone_address := x"00300000";
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(c_test_dpram_size), x"00000000"),
1 => f_sdb_embed_bridge(c_ref_bridge, x"00100000"),
2 => f_sdb_embed_bridge(c_wrcore_bridge_sdb, x"00200000"));
constant c_sdb_address : t_wishbone_address := x"00300000";
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
......@@ -725,6 +726,8 @@ begin
master_i => cbar_slave_o(0));
PCIe : pcie_wb
generic map(
sdb_addr => c_sdb_address)
port map(
clk125_i => pllout_clk_sys,
cal_clk50_i => clk_reconf,
......@@ -782,14 +785,14 @@ begin
mb_master_in.stall <= '0';
mb_master_in.dat <= std_logic_vector(to_unsigned(0,mb_master_in.dat'length-pio_reg'length)) & pio_reg;
GSI_REF_CON : xwb_sdwb_crossbar
GSI_REF_CON : xwb_sdb_crossbar
generic map(
g_num_masters => c_ref_masters,
g_num_slaves => c_ref_slaves,
g_registered => true,
g_wraparound => true,
g_layout => c_ref_layout,
g_sdwb_addr => c_ref_sdwb_address)
g_sdb_addr => c_ref_sdb_address)
port map(
clk_sys_i => clk_125m_pllref_p,
rst_n_i => nreset,
......@@ -810,14 +813,14 @@ begin
master_i => cbar_ref_slave_o(0),
master_o => cbar_ref_slave_i(0));
GSI_CON : xwb_sdwb_crossbar
GSI_CON : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true,
g_layout => c_layout,
g_sdwb_addr => c_sdwb_address)
g_sdb_addr => c_sdb_address)
port map(
clk_sys_i => pllout_clk_sys,
rst_n_i => nreset,
......
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