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White Rabbit core collection
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59e6659c
Commit
59e6659c
authored
Jun 20, 2017
by
Maciej Lipinski
Committed by
Adam Wujek
Jun 20, 2017
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[wbgen-ver] updated streamers and diags to have version of the wbgen registers
parent
4f95bf99
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2 changed files
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82 additions
and
54 deletions
+82
-54
wr_streamers.h
include/hw/wr_streamers.h
+48
-34
wrc_diags_regs.h
include/hw/wrc_diags_regs.h
+34
-20
No files found.
include/hw/wr_streamers.h
View file @
59e6659c
...
...
@@ -3,7 +3,8 @@
* File : ./doc/wr_streamers.h
* Author : auto-generated by wbgen2 from wr_streamers_wb.wb
* Created : Wed May 17 08:49:53 2017
* Created : Tue Jun 20 08:53:54 2017
* Version : 0x00000001
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
...
...
@@ -34,6 +35,17 @@
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* version definition */
#define WBGEN2_WR_STREAMERS_VERSION 0x00000001
/* definitions for register: Version register */
/* definitions for field: Version identifier in reg: Version register */
#define WR_STREAMERS_VER_ID_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_VER_ID_SHIFT 0
#define WR_STREAMERS_VER_ID_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_VER_ID_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Statistics status and ctrl register */
...
...
@@ -348,71 +360,73 @@
#define WR_STREAMERS_DUMMY_DUMMY_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
PACKED
struct
WR_STREAMERS_WB
{
/* [0x0]: REG
Statistics status and ctrl
register */
uint32_t
SSCR1
;
/* [0x0]: REG
Version
register */
uint32_t
VER
;
/* [0x4]: REG Statistics status and ctrl register */
uint32_t
SSCR
2
;
uint32_t
SSCR
1
;
/* [0x8]: REG Statistics status and ctrl register */
uint32_t
SSCR2
;
/* [0xc]: REG Statistics status and ctrl register */
uint32_t
SSCR3
;
/* [0xc]: REG Rx statistics */
uint32_t
RX_STAT0
;
/* [0x10]: REG Rx statistics */
uint32_t
RX_STAT0
;
/* [0x14]: REG Rx statistics */
uint32_t
RX_STAT1
;
/* [0x14]: REG Tx statistics */
uint32_t
TX_STAT2
;
/* [0x18]: REG Tx statistics */
uint32_t
TX_STAT2
;
/* [0x1c]: REG Tx statistics */
uint32_t
TX_STAT3
;
/* [0x1c]: REG Rx statistics */
uint32_t
RX_STAT4
;
/* [0x20]: REG Rx statistics */
uint32_t
RX_STAT
5
;
uint32_t
RX_STAT
4
;
/* [0x24]: REG Rx statistics */
uint32_t
RX_STAT
6
;
uint32_t
RX_STAT
5
;
/* [0x28]: REG Rx statistics */
uint32_t
RX_STAT
7
;
uint32_t
RX_STAT
6
;
/* [0x2c]: REG Rx statistics */
uint32_t
RX_STAT
8
;
uint32_t
RX_STAT
7
;
/* [0x30]: REG Rx statistics */
uint32_t
RX_STAT
9
;
uint32_t
RX_STAT
8
;
/* [0x34]: REG Rx statistics */
uint32_t
RX_STAT
10
;
uint32_t
RX_STAT
9
;
/* [0x38]: REG Rx statistics */
uint32_t
RX_STAT1
1
;
uint32_t
RX_STAT1
0
;
/* [0x3c]: REG Rx statistics */
uint32_t
RX_STAT1
2
;
uint32_t
RX_STAT1
1
;
/* [0x40]: REG Rx statistics */
uint32_t
RX_STAT12
;
/* [0x44]: REG Rx statistics */
uint32_t
RX_STAT13
;
/* [0x4
4
]: REG Tx Config Reg 0 */
/* [0x4
8
]: REG Tx Config Reg 0 */
uint32_t
TX_CFG0
;
/* [0x4
8
]: REG Tx Config Reg 1 */
/* [0x4
c
]: REG Tx Config Reg 1 */
uint32_t
TX_CFG1
;
/* [0x
4c
]: REG Tx Config Reg 2 */
/* [0x
50
]: REG Tx Config Reg 2 */
uint32_t
TX_CFG2
;
/* [0x5
0
]: REG Tx Config Reg 3 */
/* [0x5
4
]: REG Tx Config Reg 3 */
uint32_t
TX_CFG3
;
/* [0x54]: REG Tx Config Reg 4 */
uint32_t
TX_CFG4
;
/* [0x58]: REG Tx Config Reg 4 */
uint32_t
TX_CFG4
;
/* [0x5c]: REG Tx Config Reg 4 */
uint32_t
TX_CFG5
;
/* [0x
5c
]: REG Rx Config Reg 0 */
/* [0x
60
]: REG Rx Config Reg 0 */
uint32_t
RX_CFG0
;
/* [0x6
0
]: REG Rx Config Reg 1 */
/* [0x6
4
]: REG Rx Config Reg 1 */
uint32_t
RX_CFG1
;
/* [0x6
4
]: REG Rx Config Reg 2 */
/* [0x6
8
]: REG Rx Config Reg 2 */
uint32_t
RX_CFG2
;
/* [0x6
8
]: REG Rx Config Reg 3 */
/* [0x6
c
]: REG Rx Config Reg 3 */
uint32_t
RX_CFG3
;
/* [0x
6c
]: REG Rx Config Reg 4 */
/* [0x
70
]: REG Rx Config Reg 4 */
uint32_t
RX_CFG4
;
/* [0x7
0
]: REG Rx Config Reg 5 */
/* [0x7
4
]: REG Rx Config Reg 5 */
uint32_t
RX_CFG5
;
/* [0x7
4
]: REG TxRx Config Override */
/* [0x7
8
]: REG TxRx Config Override */
uint32_t
CFG
;
/* [0x7
8
]: REG DBG Control register */
/* [0x7
c
]: REG DBG Control register */
uint32_t
DBG_CTRL
;
/* [0x
7c
]: REG DBG Data */
/* [0x
80
]: REG DBG Data */
uint32_t
DBG_DATA
;
/* [0x8
0
]: REG Test value */
/* [0x8
4
]: REG Test value */
uint32_t
DUMMY
;
};
...
...
include/hw/wrc_diags_regs.h
View file @
59e6659c
...
...
@@ -3,7 +3,8 @@
* File : wrc_diags_regs.h
* Author : auto-generated by wbgen2 from wrc_diags_wb.wb
* Created : Mon May 8 13:58:25 2017
* Created : Tue Jun 20 09:59:03 2017
* Version : 0x00000001
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
...
...
@@ -34,6 +35,17 @@
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* version definition */
#define WBGEN2_WRC_DIAGS_VERSION 0x00000001
/* definitions for register: Version register */
/* definitions for field: Version identifier in reg: Version register */
#define WRC_DIAGS_VER_ID_MASK WBGEN2_GEN_MASK(0, 32)
#define WRC_DIAGS_VER_ID_SHIFT 0
#define WRC_DIAGS_VER_ID_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WRC_DIAGS_VER_ID_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Ctrl */
...
...
@@ -107,43 +119,45 @@
/* definitions for register: WRPC Diag: Board temperature [C degree] */
PACKED
struct
WRC_DIAGS_WB
{
/* [0x0]: REG Ctrl */
/* [0x0]: REG Version register */
uint32_t
VER
;
/* [0x4]: REG Ctrl */
uint32_t
CTRL
;
/* [0x
4
]: REG WRPC Diag: servo status */
/* [0x
8
]: REG WRPC Diag: servo status */
uint32_t
WDIAG_SSTAT
;
/* [0x
8
]: REG WRPC Diag: Port status */
/* [0x
c
]: REG WRPC Diag: Port status */
uint32_t
WDIAG_PSTAT
;
/* [0x
c
]: REG WRPC Diag: PTP state */
/* [0x
10
]: REG WRPC Diag: PTP state */
uint32_t
WDIAG_PTPSTAT
;
/* [0x1
0
]: REG WRPC Diag: AUX state */
/* [0x1
4
]: REG WRPC Diag: AUX state */
uint32_t
WDIAG_ASTAT
;
/* [0x1
4
]: REG WRPC Diag: Tx PTP Frame cnts */
/* [0x1
8
]: REG WRPC Diag: Tx PTP Frame cnts */
uint32_t
WDIAG_TXFCNT
;
/* [0x1
8
]: REG WRPC Diag: Rx PTP Frame cnts */
/* [0x1
c
]: REG WRPC Diag: Rx PTP Frame cnts */
uint32_t
WDIAG_RXFCNT
;
/* [0x
1c
]: REG WRPC Diag:local time [msb of s] */
/* [0x
20
]: REG WRPC Diag:local time [msb of s] */
uint32_t
WDIAG_SEC_MSB
;
/* [0x2
0
]: REG WRPC Diag: local time [lsb of s] */
/* [0x2
4
]: REG WRPC Diag: local time [lsb of s] */
uint32_t
WDIAG_SEC_LSB
;
/* [0x2
4
]: REG WRPC Diag: local time [ns] */
/* [0x2
8
]: REG WRPC Diag: local time [ns] */
uint32_t
WDIAG_NS
;
/* [0x2
8
]: REG WRPC Diag: Round trip (mu) [msb of ps] */
/* [0x2
c
]: REG WRPC Diag: Round trip (mu) [msb of ps] */
uint32_t
WDIAG_MU_MSB
;
/* [0x
2c
]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
/* [0x
30
]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
uint32_t
WDIAG_MU_LSB
;
/* [0x3
0
]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
/* [0x3
4
]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
uint32_t
WDIAG_DMS_MSB
;
/* [0x3
4
]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
/* [0x3
8
]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
uint32_t
WDIAG_DMS_LSB
;
/* [0x3
8
]: REG WRPC Diag: Total link asymmetry [ps] */
/* [0x3
c
]: REG WRPC Diag: Total link asymmetry [ps] */
uint32_t
WDIAG_ASYM
;
/* [0x
3c
]: REG WRPC Diag: Clock offset (cko) [ps] */
/* [0x
40
]: REG WRPC Diag: Clock offset (cko) [ps] */
uint32_t
WDIAG_CKO
;
/* [0x4
0
]: REG WRPC Diag: Phase setpoint (setp) [ps] */
/* [0x4
4
]: REG WRPC Diag: Phase setpoint (setp) [ps] */
uint32_t
WDIAG_SETP
;
/* [0x4
4
]: REG WRPC Diag: Update counter (ucnt) */
/* [0x4
8
]: REG WRPC Diag: Update counter (ucnt) */
uint32_t
WDIAG_UCNT
;
/* [0x4
8
]: REG WRPC Diag: Board temperature [C degree] */
/* [0x4
c
]: REG WRPC Diag: Board temperature [C degree] */
uint32_t
WDIAG_TEMP
;
};
...
...
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