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White Rabbit core collection
Commit 59681824 authored by Pascal Bos's avatar Pascal Bos Committed by Peter Jansweijer
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enabled processing system for write design. 

added processing system io

updated general cores for axi_wb fix

# Conflicts:
#	ip_cores/general-cores
parent b4d523f0
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Showing with 1291 additions and 35 deletions
board/spec7/wr_spec7_pkg.vhd
View file @ 59681824
......@@ -192,4 +192,74 @@ package wr_spec7_pkg is
pcie_mgt_0_txp : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component Pcie_wrapper;
component processing_system_pcie_wrapper is
port (
aclk1_0 : in STD_LOGIC;
pcie_clk : in STD_LOGIC;
pcie_rst_n : in STD_LOGIC;
user_lnk_up_0 : out STD_LOGIC;
usr_irq_ack_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
usr_irq_req_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
gpio_rtl_0_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
M00_AXI_0_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_0_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_awvalid : out STD_LOGIC;
M00_AXI_0_awready : in STD_LOGIC;
M00_AXI_0_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_wlast : out STD_LOGIC;
M00_AXI_0_wvalid : out STD_LOGIC;
M00_AXI_0_wready : in STD_LOGIC;
M00_AXI_0_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_bvalid : in STD_LOGIC;
M00_AXI_0_bready : out STD_LOGIC;
M00_AXI_0_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_0_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_0_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_0_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_0_arvalid : out STD_LOGIC;
M00_AXI_0_arready : in STD_LOGIC;
M00_AXI_0_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_0_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_0_rlast : in STD_LOGIC;
M00_AXI_0_rvalid : in STD_LOGIC;
M00_AXI_0_rready : out STD_LOGIC;
pcie_mgt_0_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
pcie_mgt_0_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
pcie_mgt_0_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
pcie_mgt_0_txp : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component processing_system_pcie_wrapper;
end wr_spec7_pkg;
general-cores @ a53c3b85
Subproject commit f73bc3d2959bdaab52adf910d99ed90cabab11ab
Subproject commit a53c3b8503c0bdd3a57eed1401b5b8fc38b7be8b
platform/xilinx/wr_pcie/processing_system_pcie.tcl 0 → 100644
View file @ 59681824
This diff is collapsed.
top/spec7_write_design/spec7_write_top.vhd
View file @ 59681824
......@@ -183,7 +183,33 @@ entity spec7_write_top is
rxn : in std_logic_vector(1 downto 0);
rxp : in std_logic_vector(1 downto 0);
txn : out std_logic_vector(1 downto 0);
txp : out std_logic_vector(1 downto 0)
txp : out std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- Processing System interface
---------------------------------------------------------------------------
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end entity spec7_write_top;
......@@ -304,47 +330,69 @@ pci_clk_buf : IBUFDS_GTE2
ODIV2 => open,
CEB => '0'
);
Pcie: Pcie_wrapper
Pcie: processing_system_pcie_wrapper
port map (
DDR_addr =>DDR_addr ,
DDR_ba =>DDR_ba ,
DDR_cas_n =>DDR_cas_n ,
DDR_ck_n =>DDR_ck_n ,
DDR_ck_p =>DDR_ck_p ,
DDR_cke =>DDR_cke ,
DDR_cs_n =>DDR_cs_n ,
DDR_dm =>DDR_dm ,
DDR_dq =>DDR_dq ,
DDR_dqs_n =>DDR_dqs_n ,
DDR_dqs_p =>DDR_dqs_p ,
DDR_odt =>DDR_odt ,
DDR_ras_n =>DDR_ras_n ,
DDR_reset_n =>DDR_reset_n ,
DDR_we_n =>DDR_we_n ,
FIXED_IO_ddr_vrn =>FIXED_IO_ddr_vrn ,
FIXED_IO_ddr_vrp =>FIXED_IO_ddr_vrp ,
FIXED_IO_mio =>FIXED_IO_mio ,
FIXED_IO_ps_clk =>FIXED_IO_ps_clk ,
FIXED_IO_ps_porb =>FIXED_IO_ps_porb ,
FIXED_IO_ps_srstb =>FIXED_IO_ps_srstb,
M00_AXI_0_araddr => m_axil_o.araddr,
M00_AXI_0_arburst => open,
M00_AXI_0_arcache => open,
M00_AXI_0_arlen => open,
M00_AXI_0_arlock => open,
M00_AXI_0_arprot => open,
M00_AXI_0_arqos => open,
M00_AXI_0_arready => m_axil_i.arready,
M00_AXI_0_arsize => open,
M00_AXI_0_arburst => open,
M00_AXI_0_arcache => open,
M00_AXI_0_arlen => open,
M00_AXI_0_arlock => open,
M00_AXI_0_arprot => open,
M00_AXI_0_arqos => open,
M00_AXI_0_arready => m_axil_i.arready,
M00_AXI_0_arsize => open,
M00_AXI_0_arvalid => m_axil_o.arvalid,
M00_AXI_0_awaddr => m_axil_o.awaddr,
M00_AXI_0_awburst => open,
M00_AXI_0_awcache => open,
M00_AXI_0_awlen => open,
M00_AXI_0_awlock => open,
M00_AXI_0_awprot => open,
M00_AXI_0_awqos => open,
M00_AXI_0_awready => m_axil_i.awready,
M00_AXI_0_awsize => open,
M00_AXI_0_awvalid => m_axil_o.awvalid,
M00_AXI_0_bready => m_axil_o.bready,
M00_AXI_0_bresp => m_axil_i.bresp,
M00_AXI_0_bvalid => m_axil_i.bvalid,
M00_AXI_0_rdata => m_axil_i.rdata,
M00_AXI_0_rlast => m_axil_i.rlast,
M00_AXI_0_rready => m_axil_o.rready,
M00_AXI_0_rresp => m_axil_i.rresp,
M00_AXI_0_rvalid => m_axil_i.rvalid,
M00_AXI_0_wdata => m_axil_o.wdata,
M00_AXI_0_wlast => m_axil_o.wlast,
M00_AXI_0_wready => m_axil_i.wready,
M00_AXI_0_wstrb => m_axil_o.wstrb,
M00_AXI_0_wvalid => m_axil_o.wvalid,
M00_AXI_0_awaddr => m_axil_o.awaddr,
M00_AXI_0_awburst => open,
M00_AXI_0_awcache => open,
M00_AXI_0_awlen => open,
M00_AXI_0_awlock => open,
M00_AXI_0_awprot => open,
M00_AXI_0_awqos => open,
M00_AXI_0_awready => m_axil_i.awready,
M00_AXI_0_awsize => open,
M00_AXI_0_awvalid => m_axil_o.awvalid,
M00_AXI_0_bready => m_axil_o.bready,
M00_AXI_0_bresp => m_axil_i.bresp,
M00_AXI_0_bvalid => m_axil_i.bvalid,
M00_AXI_0_rdata => m_axil_i.rdata,
M00_AXI_0_rlast => m_axil_i.rlast,
M00_AXI_0_rready => m_axil_o.rready,
M00_AXI_0_rresp => m_axil_i.rresp,
M00_AXI_0_rvalid => m_axil_i.rvalid,
M00_AXI_0_wdata => m_axil_o.wdata,
M00_AXI_0_wlast => m_axil_o.wlast,
M00_AXI_0_wready => m_axil_i.wready,
M00_AXI_0_wstrb => m_axil_o.wstrb,
M00_AXI_0_wvalid => m_axil_o.wvalid,
aclk1_0 => clk_sys_62m5,
gpio_rtl_0_tri_o => open,
pcie_clk => pci_clk,
pcie_mgt_0_rxn => rxn,
pcie_mgt_0_rxp => rxp,
pcie_mgt_0_txn => txn,
pcie_mgt_0_txp => txp,
pcie_clk => pci_clk,
pcie_rst_n => perst_n,
user_lnk_up_0 => open,
usr_irq_ack_0 => open,
......
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