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White Rabbit core collection
Commits
594311bb
Commit
594311bb
authored
Aug 16, 2017
by
Grzegorz Daniluk
Browse files
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regenerate wb interfaces to reduce warnings
parent
187d4f03
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Showing
11 changed files
with
22 additions
and
72 deletions
+22
-72
ep_pcs_tbi_mdio_wb.vhd
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+2
-12
ep_registers_pkg.vhd
modules/wr_endpoint/ep_registers_pkg.vhd
+1
-1
ep_wishbone_controller.vhd
modules/wr_endpoint/ep_wishbone_controller.vhd
+2
-12
minic_wb_slave.vhd
modules/wr_mini_nic/minic_wb_slave.vhd
+2
-12
minic_wbgen2_pkg.vhd
modules/wr_mini_nic/minic_wbgen2_pkg.vhd
+1
-1
pps_gen_regs.h
modules/wr_pps_gen/pps_gen_regs.h
+1
-1
pps_gen_wb.vhd
modules/wr_pps_gen/pps_gen_wb.vhd
+2
-12
spll_wb_slave.vhd
modules/wr_softpll_ng/spll_wb_slave.vhd
+2
-12
spll_wbgen2_pkg.vhd
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
+4
-4
wr_streamers_wb.vhd
modules/wr_streamers/wr_streamers_wb.vhd
+1
-1
wr_streamers_wbgen2_pkg.vhd
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
+4
-4
No files found.
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created :
Thu Aug 6 09:50:34 2015
-- Created :
Wed Aug 16 22:43:42 2017
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
...
@@ -120,22 +120,12 @@ signal mdio_ectrl_tx_prbs_sel_int : std_logic_vector(2 downto 0);
...
@@ -120,22 +120,12 @@ signal mdio_ectrl_tx_prbs_sel_int : std_logic_vector(2 downto 0);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
4
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
4
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
begin
-- Some internal signals assignments
. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
--
-- Main register bank access process.
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
...
...
modules/wr_endpoint/ep_registers_pkg.vhd
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created :
Thu Aug 6 15:57:28 2015
-- Created :
Wed Aug 16 22:43:41 2017
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
...
...
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created :
Thu Aug 6 15:57:28 2015
-- Created :
Wed Aug 16 22:43:41 2017
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
...
@@ -83,22 +83,12 @@ signal ep_mdio_asr_phyad_int : std_logic_vector(7 downto 0);
...
@@ -83,22 +83,12 @@ signal ep_mdio_asr_phyad_int : std_logic_vector(7 downto 0);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
4
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
4
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
begin
-- Some internal signals assignments
. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
--
-- Main register bank access process.
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
...
...
modules/wr_mini_nic/minic_wb_slave.vhd
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : minic_wb_slave.vhd
-- File : minic_wb_slave.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Wed
Oct 26 11:30:27 2016
-- Created : Wed
Aug 16 22:41:57 2017
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
...
@@ -65,22 +65,12 @@ signal irq_inputs_vector_int : std_logic_vector(2 downto 0);
...
@@ -65,22 +65,12 @@ signal irq_inputs_vector_int : std_logic_vector(2 downto 0);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
4
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
4
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
begin
-- Some internal signals assignments
. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
--
-- Main register bank access process.
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
...
...
modules/wr_mini_nic/minic_wbgen2_pkg.vhd
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : minic_wbgen2_pkg.vhd
-- File : minic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Wed
Oct 26 11:30:27 2016
-- Created : Wed
Aug 16 22:41:57 2017
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
...
...
modules/wr_pps_gen/pps_gen_regs.h
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
* File : pps_gen_regs.h
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Author : auto-generated by wbgen2 from pps_gen_wb.wb
* Created :
Fri Feb 10 10:53:05
2017
* Created :
Wed Aug 16 22:41:09
2017
* Standard : ANSI C
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
...
...
modules/wr_pps_gen/pps_gen_wb.vhd
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : pps_gen_wb.vhd
-- File : pps_gen_wb.vhd
-- Author : auto-generated by wbgen2 from pps_gen_wb.wb
-- Author : auto-generated by wbgen2 from pps_gen_wb.wb
-- Created :
Fri Feb 10 10:53:05
2017
-- Created :
Wed Aug 16 22:41:09
2017
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
...
@@ -154,22 +154,12 @@ signal ppsg_escr_nsec_set_sync2 : std_logic ;
...
@@ -154,22 +154,12 @@ signal ppsg_escr_nsec_set_sync2 : std_logic ;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
2
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
2
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
begin
-- Some internal signals assignments
. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
--
-- Main register bank access process.
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
...
...
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created :
Thu Apr 20 16:40:20
2017
-- Created :
Wed Aug 16 22:42:41
2017
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
...
@@ -73,22 +73,12 @@ signal irq_inputs_vector_int : std_logic_vector(0 downto 0);
...
@@ -73,22 +73,12 @@ signal irq_inputs_vector_int : std_logic_vector(0 downto 0);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
5
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
5
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
begin
-- Some internal signals assignments
. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
--
-- Main register bank access process.
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
...
...
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created :
Thu Apr 20 16:40:20
2017
-- Created :
Wed Aug 16 22:42:41
2017
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
...
@@ -165,10 +165,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
...
@@ -165,10 +165,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
begin
for
i
in
0
to
x
'length
-1
loop
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U'
)
then
if
x
(
i
)
=
'1'
then
tmp
(
i
):
=
'
0
'
;
tmp
(
i
):
=
'
1
'
;
else
else
tmp
(
i
):
=
x
(
i
)
;
tmp
(
i
):
=
'0'
;
end
if
;
end
if
;
end
loop
;
end
loop
;
return
tmp
;
return
tmp
;
...
...
modules/wr_streamers/wr_streamers_wb.vhd
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : wr_streamers_wb.vhd
-- File : wr_streamers_wb.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created :
Tue Jun 20 08:53:54
2017
-- Created :
Wed Aug 16 22:45:12
2017
-- Version : 0x00000001
-- Version : 0x00000001
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
...
...
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @
594311bb
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd
-- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created :
Tue Jun 20 08:53:54
2017
-- Created :
Wed Aug 16 22:45:12
2017
-- Version : 0x00000001
-- Version : 0x00000001
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
...
@@ -155,10 +155,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
...
@@ -155,10 +155,10 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
begin
for
i
in
0
to
x
'length
-1
loop
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U'
)
then
if
x
(
i
)
=
'1'
then
tmp
(
i
):
=
'
0
'
;
tmp
(
i
):
=
'
1
'
;
else
else
tmp
(
i
):
=
x
(
i
)
;
tmp
(
i
):
=
'0'
;
end
if
;
end
if
;
end
loop
;
end
loop
;
return
tmp
;
return
tmp
;
...
...
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