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White Rabbit core collection
Commit 56e068f9 authored by Maciej Lipinski's avatar Maciej Lipinski
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update of the xwr_transmission to make it properly generic and flexible: 

- added generics that are availabel in the tx/rx stremeamer module and wb_adapter
- added overriding of tx/rx cfg (local/remote/target MAC, ethertype) from WB-regs
- added input tx/rx cfg signals
parent 5385ec30
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Showing with 820 additions and 141 deletions
modules/wr_streamers/streamers_pkg.vhd
View file @ 56e068f9
......@@ -112,36 +112,115 @@ package streamers_pkg is
constant c_WR_TRANS_ARR_SIZE_IN : integer := c_STREAMERS_ARR_SIZE_IN;
component xwr_transmission is
generic (
g_tx_data_width : integer := 32;
g_rx_data_width : integer := 32
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
tx_data_i : in std_logic_vector(g_tx_data_width-1 downto 0);
tx_valid_i : in std_logic;
tx_dreq_o : out std_logic;
tx_last_p1_i : in std_logic := '1';
tx_flush_p1_i : in std_logic := '0';
rx_first_p1_o : out std_logic;
rx_last_p1_o : out std_logic;
rx_data_o : out std_logic_vector(g_rx_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
clk_ref_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
snmp_array_o : out t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_WR_TRANS_ARR_SIZE_IN -1 downto 0)
);
generic (
-----------------------------------------------------------------------------------------
-- Transmission (tx)
-----------------------------------------------------------------------------------------
-- Width of data words on tx_data_i.
g_tx_data_width : integer := 32;
-- Minimum number of data words in the TX buffer that will trigger transmission of an
-- Ethernet frame. Also defines the buffer size (2 * g_tx_threshold). Note
-- that in order for a frame to be transmitted, the buffer must conatain at
-- least one complete block.
g_tx_threshold : integer := 128;
-- Maximum number of data words in a single Ethernet frame. It also defines
-- the maximum block size (since blocks can't be currently split across
-- multiple frames).
g_tx_max_words_per_frame : integer := 128;
-- Transmission timeout (in clk_sys_i cycles), after which the contents
-- of TX buffer are sent regardless of the amount of data that is currently
-- stored in the buffer, so that data in the buffer does not get stuck.
g_tx_timeout : integer := 1024;
-- DO NOT USE unless you know what you are doing
-- legacy stuff: the streamers initially used in Btrain did not check/insert the escape
-- code. This is justified if only one block of a known number of words is sent/expected
g_tx_escape_code_disable : boolean := FALSE;
-----------------------------------------------------------------------------------------
-- Reception (rx)
-----------------------------------------------------------------------------------------
-- Width of the data words. Must be same as in the TX streamer.
g_rx_data_width : integer := 32;
-- Size of RX buffer, in data words.
g_rx_buffer_size : integer := 16;
-- When true, receives only packets whose destination MAC equals
-- cfg_mac_remote_i. When false. accepts all incoming packets.
g_rx_filter_remote_mac : boolean := false;
-- DO NOT USE unless you know what you are doing
-- legacy stuff: the streamers that were initially used in Btrain did not check/insert
-- the escape code. This is justified if only one block of a known number of words is
-- sent/expected.
g_rx_escape_code_disable : boolean := FALSE;
-- DO NOT USE unless you know what you are doing
-- legacy stuff: the streamers that were initially used in Btrain accepted only a fixed
-- number of words, regardless of the frame content. If this generic is set to number
-- other than zero, only a fixed number of words is accepted.
-- In combination with the g_escape_code_disable generic set to TRUE, the behaviour of
-- the "Btrain streamers" can be recreated.
g_rx_expected_words_number : integer := 0;
-----------------------------------------------------------------------------------------
-- Statistics config
-----------------------------------------------------------------------------------------
-- width of counters: frame rx/tx/lost, block lost, counter of accumuted latency
-- (minimum 15 bits, max 32)
g_stats_cnt_width : integer := 32;
-- width of latency accumulator (max value 64)
g_stats_acc_width : integer := 64;
-----------------------------------------------------------------------------------------
-- WB I/F configuration
-----------------------------------------------------------------------------------------
g_slave_mode : t_wishbone_interface_mode := CLASSIC;
g_slave_granularity : t_wishbone_address_granularity := BYTE
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- WR tx/rx interface
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
-- User tx interface
tx_data_i : in std_logic_vector(g_tx_data_width-1 downto 0);
tx_valid_i : in std_logic;
tx_dreq_o : out std_logic;
tx_last_p1_i : in std_logic := '1';
tx_flush_p1_i : in std_logic := '0';
-- User rx interface
rx_first_p1_o : out std_logic;
rx_last_p1_o : out std_logic;
rx_data_o : out std_logic_vector(g_rx_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
-- WRC Timing interface, used for latency measurement
clk_ref_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
snmp_array_o : out t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_WR_TRANS_ARR_SIZE_IN -1 downto 0);
-- Transmission (tx) configuration
tx_cfg_mac_local_i : in std_logic_vector(47 downto 0) := x"000000000000";
tx_cfg_mac_target_i : in std_logic_vector(47 downto 0):= x"ffffffffffff";
tx_cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff";
-- Reception (rx)configuration
rx_cfg_mac_local_i : in std_logic_vector(47 downto 0) := x"000000000000";
rx_cfg_mac_remote_i : in std_logic_vector(47 downto 0) := x"000000000000";
rx_cfg_ethertype_i : in std_logic_vector(15 downto 0) := x"dbff";
rx_cfg_accept_broadcasts_i : in std_logic := '1'
);
end component;
end streamers_pkg;
\ No newline at end of file
modules/wr_streamers/wr_transmission_wb.vhd
View file @ 56e068f9
This diff is collapsed.
modules/wr_streamers/wr_transmission_wb.wb
View file @ 56e068f9
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Transmission control and debug";
name = "WR Transmission control, status and debug";
description = "\
-----------------------------------------------------------------\
This WB registers allow to diagnose transmission and reception of\
......@@ -208,6 +208,159 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "Tx Config Reg 0";
prefix = "TX_CFG0";
field {
name = "Ethertype";
prefix = "Ethertype";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Tx Config Reg 1";
prefix = "TX_CFG1";
field {
name = "MAC Local LSB";
prefix = "mac_local_LSB";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Tx Config Reg 2";
prefix = "TX_CFG2";
field {
name = "MAC Local MSB";
prefix = "mac_local_MSB";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Tx Config Reg 3";
prefix = "TX_CFG3";
field {
name = "MAC Target LSB";
prefix = "mac_target_lsb";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Tx Config Reg 4";
prefix = "TX_CFG4";
field {
name = "MAC Target MSB";
prefix = "mac_target_MSB";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Rx Config Reg 0";
prefix = "RX_CFG0";
field {
name = "Ethertype";
prefix = "Ethertype";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Accept Broadcast";
description = "0: accept only unicasts; \
1: accept all broadcast packets";
prefix = "accept_broadcast";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Rx Config Reg 1";
prefix = "RX_CFG1";
field {
name = "MAC Local LSB";
prefix = "mac_local_LSB";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Rx Config Reg 2";
prefix = "RX_CFG2";
field {
name = "MAC Local MSB";
prefix = "mac_local_MSB";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Rx Config Reg 3";
prefix = "RX_CFG3";
field {
name = "MAC Remote LSB";
prefix = "mac_remote_lsb";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Rx Config Reg 4";
prefix = "RX_CFG4";
field {
name = "MAC Remote MSB";
prefix = "mac_remote_MSB";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TxRx Config";
prefix = "CFG";
field {
name = "Enable WB TX CONFIG";
description = "Decide whether the transmission configuration of streamers should be the one provided as an input to the xwr_transmission module (either default, or provided by application-specifici module) or it should be the one provided in the WB registers:\
0: TX config loaded from application or default; \
1: TX config loaded from wishbone registers";
prefix = "tx_ena";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Enable WB RX CONFIG";
description = "Decide whether the reception configuration of streamers should be the one provided as an input to the xwr_transmission module (either default, or provided by application-specifici module) or it should be the one provided in the WB registers:\
0: RX config loaded from application or default; \
1: RX config loaded from wishbone registers";
prefix = "rx_ena";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DBG Control register";
prefix = "DBG_CTRL";
......
modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd
View file @ 56e068f9
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Transmission control and debug
-- Title : Wishbone slave core for WR Transmission control, status and debug
---------------------------------------------------------------------------------------
-- File : wr_transmission_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created : Thu Jul 28 16:59:59 2016
-- Created : Mon Nov 21 12:09:16 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
......@@ -63,6 +63,19 @@ package wr_transmission_wbgen2_pkg is
sscr1_rst_stats_o : std_logic;
sscr1_rst_seq_id_o : std_logic;
sscr1_snapshot_stats_o : std_logic;
tx_cfg0_ethertype_o : std_logic_vector(15 downto 0);
tx_cfg1_mac_local_lsb_o : std_logic_vector(31 downto 0);
tx_cfg2_mac_local_msb_o : std_logic_vector(15 downto 0);
tx_cfg3_mac_target_lsb_o : std_logic_vector(31 downto 0);
tx_cfg4_mac_target_msb_o : std_logic_vector(15 downto 0);
rx_cfg0_ethertype_o : std_logic_vector(15 downto 0);
rx_cfg0_accept_broadcast_o : std_logic;
rx_cfg1_mac_local_lsb_o : std_logic_vector(31 downto 0);
rx_cfg2_mac_local_msb_o : std_logic_vector(15 downto 0);
rx_cfg3_mac_remote_lsb_o : std_logic_vector(31 downto 0);
rx_cfg4_mac_remote_msb_o : std_logic_vector(15 downto 0);
cfg_tx_ena_o : std_logic;
cfg_rx_ena_o : std_logic;
dbg_ctrl_mux_o : std_logic;
dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0);
end record;
......@@ -71,6 +84,19 @@ package wr_transmission_wbgen2_pkg is
sscr1_rst_stats_o => '0',
sscr1_rst_seq_id_o => '0',
sscr1_snapshot_stats_o => '0',
tx_cfg0_ethertype_o => (others => '0'),
tx_cfg1_mac_local_lsb_o => (others => '0'),
tx_cfg2_mac_local_msb_o => (others => '0'),
tx_cfg3_mac_target_lsb_o => (others => '0'),
tx_cfg4_mac_target_msb_o => (others => '0'),
rx_cfg0_ethertype_o => (others => '0'),
rx_cfg0_accept_broadcast_o => '0',
rx_cfg1_mac_local_lsb_o => (others => '0'),
rx_cfg2_mac_local_msb_o => (others => '0'),
rx_cfg3_mac_remote_lsb_o => (others => '0'),
rx_cfg4_mac_remote_msb_o => (others => '0'),
cfg_tx_ena_o => '0',
cfg_rx_ena_o => '0',
dbg_ctrl_mux_o => '0',
dbg_ctrl_start_byte_o => (others => '0')
);
......
modules/wr_streamers/xwr_transmission.vhd
View file @ 56e068f9
This diff is collapsed.
sim/wr_transmission_wb.svh
View file @ 56e068f9
`define ADDR_WR_TRANSMISSION_SSCR1 6'h0
`define ADDR_WR_TRANSMISSION_SSCR1 7'h0
`define WR_TRANSMISSION_SSCR1_RST_STATS_OFFSET 0
`define WR_TRANSMISSION_SSCR1_RST_STATS 32'h00000001
`define WR_TRANSMISSION_SSCR1_RST_SEQ_ID_OFFSET 1
......@@ -9,44 +9,81 @@
`define WR_TRANSMISSION_SSCR1_RX_LATENCY_ACC_OVERFLOW 32'h00000008
`define WR_TRANSMISSION_SSCR1_RST_TS_CYC_OFFSET 4
`define WR_TRANSMISSION_SSCR1_RST_TS_CYC 32'hfffffff0
`define ADDR_WR_TRANSMISSION_SSCR2 6'h4
`define ADDR_WR_TRANSMISSION_SSCR2 7'h4
`define WR_TRANSMISSION_SSCR2_RST_TS_TAI_LSB_OFFSET 0
`define WR_TRANSMISSION_SSCR2_RST_TS_TAI_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_TX_STAT 6'h8
`define ADDR_WR_TRANSMISSION_TX_STAT 7'h8
`define WR_TRANSMISSION_TX_STAT_TX_SENT_CNT_OFFSET 0
`define WR_TRANSMISSION_TX_STAT_TX_SENT_CNT 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT1 6'hc
`define ADDR_WR_TRANSMISSION_RX_STAT1 7'hc
`define WR_TRANSMISSION_RX_STAT1_RX_RCVD_CNT_OFFSET 0
`define WR_TRANSMISSION_RX_STAT1_RX_RCVD_CNT 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT2 6'h10
`define ADDR_WR_TRANSMISSION_RX_STAT2 7'h10
`define WR_TRANSMISSION_RX_STAT2_RX_LOSS_CNT_OFFSET 0
`define WR_TRANSMISSION_RX_STAT2_RX_LOSS_CNT 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT3 6'h14
`define ADDR_WR_TRANSMISSION_RX_STAT3 7'h14
`define WR_TRANSMISSION_RX_STAT3_RX_LATENCY_MAX_OFFSET 0
`define WR_TRANSMISSION_RX_STAT3_RX_LATENCY_MAX 32'h0fffffff
`define ADDR_WR_TRANSMISSION_RX_STAT4 6'h18
`define ADDR_WR_TRANSMISSION_RX_STAT4 7'h18
`define WR_TRANSMISSION_RX_STAT4_RX_LATENCY_MIN_OFFSET 0
`define WR_TRANSMISSION_RX_STAT4_RX_LATENCY_MIN 32'h0fffffff
`define ADDR_WR_TRANSMISSION_RX_STAT5 6'h1c
`define ADDR_WR_TRANSMISSION_RX_STAT5 7'h1c
`define WR_TRANSMISSION_RX_STAT5_RX_LATENCY_ACC_LSB_OFFSET 0
`define WR_TRANSMISSION_RX_STAT5_RX_LATENCY_ACC_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT6 6'h20
`define ADDR_WR_TRANSMISSION_RX_STAT6 7'h20
`define WR_TRANSMISSION_RX_STAT6_RX_LATENCY_ACC_MSB_OFFSET 0
`define WR_TRANSMISSION_RX_STAT6_RX_LATENCY_ACC_MSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT7 6'h24
`define ADDR_WR_TRANSMISSION_RX_STAT7 7'h24
`define WR_TRANSMISSION_RX_STAT7_RX_LATENCY_ACC_CNT_OFFSET 0
`define WR_TRANSMISSION_RX_STAT7_RX_LATENCY_ACC_CNT 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_STAT8 6'h28
`define ADDR_WR_TRANSMISSION_RX_STAT8 7'h28
`define WR_TRANSMISSION_RX_STAT8_RX_LOST_BLOCK_CNT_OFFSET 0
`define WR_TRANSMISSION_RX_STAT8_RX_LOST_BLOCK_CNT 32'hffffffff
`define ADDR_WR_TRANSMISSION_DBG_CTRL 6'h2c
`define ADDR_WR_TRANSMISSION_TX_CFG0 7'h2c
`define WR_TRANSMISSION_TX_CFG0_ETHERTYPE_OFFSET 0
`define WR_TRANSMISSION_TX_CFG0_ETHERTYPE 32'h0000ffff
`define ADDR_WR_TRANSMISSION_TX_CFG1 7'h30
`define WR_TRANSMISSION_TX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_TRANSMISSION_TX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_TX_CFG2 7'h34
`define WR_TRANSMISSION_TX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_TRANSMISSION_TX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_TRANSMISSION_TX_CFG3 7'h38
`define WR_TRANSMISSION_TX_CFG3_MAC_TARGET_LSB_OFFSET 0
`define WR_TRANSMISSION_TX_CFG3_MAC_TARGET_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_TX_CFG4 7'h3c
`define WR_TRANSMISSION_TX_CFG4_MAC_TARGET_MSB_OFFSET 0
`define WR_TRANSMISSION_TX_CFG4_MAC_TARGET_MSB 32'h0000ffff
`define ADDR_WR_TRANSMISSION_RX_CFG0 7'h40
`define WR_TRANSMISSION_RX_CFG0_ETHERTYPE_OFFSET 0
`define WR_TRANSMISSION_RX_CFG0_ETHERTYPE 32'h0000ffff
`define WR_TRANSMISSION_RX_CFG0_ACCEPT_BROADCAST_OFFSET 16
`define WR_TRANSMISSION_RX_CFG0_ACCEPT_BROADCAST 32'h00010000
`define ADDR_WR_TRANSMISSION_RX_CFG1 7'h44
`define WR_TRANSMISSION_RX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_TRANSMISSION_RX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_CFG2 7'h48
`define WR_TRANSMISSION_RX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_TRANSMISSION_RX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_TRANSMISSION_RX_CFG3 7'h4c
`define WR_TRANSMISSION_RX_CFG3_MAC_REMOTE_LSB_OFFSET 0
`define WR_TRANSMISSION_RX_CFG3_MAC_REMOTE_LSB 32'hffffffff
`define ADDR_WR_TRANSMISSION_RX_CFG4 7'h50
`define WR_TRANSMISSION_RX_CFG4_MAC_REMOTE_MSB_OFFSET 0
`define WR_TRANSMISSION_RX_CFG4_MAC_REMOTE_MSB 32'h0000ffff
`define ADDR_WR_TRANSMISSION_CFG 7'h54
`define WR_TRANSMISSION_CFG_TX_ENA_OFFSET 0
`define WR_TRANSMISSION_CFG_TX_ENA 32'h00000001
`define WR_TRANSMISSION_CFG_RX_ENA_OFFSET 1
`define WR_TRANSMISSION_CFG_RX_ENA 32'h00000002
`define ADDR_WR_TRANSMISSION_DBG_CTRL 7'h58
`define WR_TRANSMISSION_DBG_CTRL_MUX_OFFSET 0
`define WR_TRANSMISSION_DBG_CTRL_MUX 32'h00000001
`define WR_TRANSMISSION_DBG_CTRL_START_BYTE_OFFSET 8
`define WR_TRANSMISSION_DBG_CTRL_START_BYTE 32'h0000ff00
`define ADDR_WR_TRANSMISSION_DBG_DATA 6'h30
`define ADDR_WR_TRANSMISSION_DBG_RX_BVALUE 6'h34
`define ADDR_WR_TRANSMISSION_DBG_TX_BVALUE 6'h38
`define ADDR_WR_TRANSMISSION_DUMMY 6'h3c
`define ADDR_WR_TRANSMISSION_DBG_DATA 7'h5c
`define ADDR_WR_TRANSMISSION_DBG_RX_BVALUE 7'h60
`define ADDR_WR_TRANSMISSION_DBG_TX_BVALUE 7'h64
`define ADDR_WR_TRANSMISSION_DUMMY 7'h68
`define WR_TRANSMISSION_DUMMY_DUMMY_OFFSET 0
`define WR_TRANSMISSION_DUMMY_DUMMY 32'hffffffff
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