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White Rabbit core collection
Commit 451ebad1 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_minic: working TX path

parent 2ec01ad9
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Showing with 212 additions and 202 deletions
modules/wr_mini_nic/Manifest.py
View file @ 451ebad1
files = [ "minic_packet_buffer.vhd",
"minic_wb_slave.vhd",
"minic_wbgen2_pkg.vhd",
"wr_mini_nic.vhd" ];
modules/wr_mini_nic/build_wb.sh
View file @ 451ebad1
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/minic.html -V minic_wb_slave.vhd -p minic_wbgen2_pkg.vhd --cstyle defines --lang vhdl -H record -K ../../sim/minic_regs.v mini_nic.wb
\ No newline at end of file
wbgen2 -D ./doc/minic.html -V minic_wb_slave.vhd -p minic_wbgen2_pkg.vhd --cstyle defines --lang vhdl -H record -K ../../sim/minic_regs.vh mini_nic.wb
\ No newline at end of file
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ 451ebad1
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wb_slave.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Mon Oct 24 14:15:09 2011
-- Created : Mon Oct 24 18:21:19 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -48,6 +48,7 @@ architecture syn of minic_wb_slave is
signal minic_mcr_tx_start_dly0 : std_logic ;
signal minic_mcr_tx_start_int : std_logic ;
signal minic_mcr_rx_en_int : std_logic ;
signal minic_mcr_rx_class_int : std_logic_vector(7 downto 0);
signal eic_idr_int : std_logic_vector(2 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(2 downto 0);
......@@ -89,6 +90,7 @@ begin
rddata_reg <= "00000000000000000000000000000000";
minic_mcr_tx_start_int <= '0';
minic_mcr_rx_en_int <= '0';
minic_mcr_rx_class_int <= "00000000";
regs_o.tx_addr_load_o <= '0';
regs_o.rx_addr_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
......@@ -129,6 +131,7 @@ begin
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
minic_mcr_rx_en_int <= wrdata_reg(10);
minic_mcr_rx_class_int <= wrdata_reg(23 downto 16);
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= regs_i.mcr_tx_idle_i;
......@@ -136,6 +139,7 @@ begin
rddata_reg(8) <= regs_i.mcr_rx_ready_i;
rddata_reg(9) <= regs_i.mcr_rx_full_i;
rddata_reg(10) <= minic_mcr_rx_en_int;
rddata_reg(23 downto 16) <= minic_mcr_rx_class_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
......@@ -146,14 +150,6 @@ begin
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -440,6 +436,8 @@ begin
-- RX DMA buffer full
-- RX DMA enable
regs_o.mcr_rx_en_o <= minic_mcr_rx_en_int;
-- RX Accepted Packet Classes
regs_o.mcr_rx_class_o <= minic_mcr_rx_class_int;
-- TX DMA buffer address
regs_o.tx_addr_o <= wrdata_reg(23 downto 0);
-- RX DMA buffer address
......
modules/wr_mini_nic/wr_mini_nic.vhd
View file @ 451ebad1
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