Skip to content

W
White Rabbit core collection
Commit 3acd992e authored by Harvey Leicester's avatar Harvey Leicester
Browse files
Options

added simple sfp control interface

parent ebb878da
Pipeline #5214 failed with stage
    Hide whitespace changes
    Inline Side-by-side
    Showing with 672 additions and 0 deletions
    modules/wr_sfp_ctrl/Manifest.py 0 → 100644
    View file @ 3acd992e
    files = [
    "sfp_ctrl_if_wb.vhd",
    "wr_sfp_ctrl.vhd",
    "xwr_sfp_ctrl.vhd",
    ]
    modules/wr_sfp_ctrl/sfp_ctrl_if_wb.cheby 0 → 100644
    View file @ 3acd992e
    memory-map:
    name: sfp_ctrl_if_wb
    description: sfp control interface
    bus: wb-32-be
    schema-version:
    core: 2.0.0
    x-conversions: 1.0.0
    x-driver-edge: 1.0.0
    x-enums: 1.0.0
    x-fesa: 2.0.0
    x-gena: 2.0.0
    x-hdl: 1.0.0
    x-map-info: 1.0.0
    x-hdl:
    iogroup: sfp_if_regs
    children:
    - reg:
    name: gpo0
    description: general purpose output register 0 (ports 0 to 7). nibbles [(N*4)-1:(N*4)] = x & led_synced_N & led_mode_N & tx_disable_N
    address: 32
    width: 32
    access: rw
    children:
    - field:
    name: gpo0_word
    comment: gpo settings for ports 0 to 7
    range: 31-0
    - reg:
    name: gpi0
    description: general purpose input register 0 (ports 0 to 7). nibbles [(N*4)-1:(N*4)] = x & los_N & detect_N & tx_fault_N
    width: 32
    access: ro
    children:
    - field:
    name: gpi0_word
    comment: gpi settings for ports 0 to 7
    range: 31-0
    - reg:
    name: gpo1
    description: general purpose output register 1 (ports 8 to 15). nibbles [(N*4)-1:(N*4)] = x & led_synced_N & led_mode_N & tx_disable_N
    width: 32
    access: rw
    children:
    - field:
    name: gpo1_word
    comment: gpo settings for ports 8 to 15
    range: 31-0
    - reg:
    name: gpi1
    description: general purpose input register 1 (ports 8 to 15). nibbles [(N*4)-1:(N*4)] = x & los_N & detect_N & tx_fault_N
    width: 32
    access: ro
    children:
    - field:
    name: gpi1_word
    comment: gpi settings for ports 8 to 15
    range: 31-0
    - reg:
    name: gpo2
    description: general purpose output register 1 (ports 16 to 23). nibbles [(N*4)-1:(N*4)] = x & led_synced_N & led_mode_N & tx_disable_N
    width: 32
    access: rw
    children:
    - field:
    name: gpo2_word
    comment: gpo settings for ports 16 to 23
    range: 31-0
    - reg:
    name: gpi2
    description: general purpose input register 0 (ports 16 to 23). nibbles [(N*4)-1:(N*4)] = x & los_N & detect_N & tx_fault_N
    width: 32
    access: ro
    children:
    - field:
    name: gpi2_word
    comment: gpi settings for ports 16 to 23
    range: 31-0
    modules/wr_sfp_ctrl/sfp_ctrl_if_wb.vhd 0 → 100644
    View file @ 3acd992e
    -- Do not edit. Generated by cheby 1.6.dev0 using these options:
    -- --gen-hdl=sfp_ctrl_if_wb.vhd -i sfp_ctrl_if_wb.cheby
    -- Generated on Mon Mar 11 08:30:59 2024 by harvey
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    package sfp_ctrl_if_wb_pkg is
    type t_sfp_if_regs_master_out is record
    gpo0_gpo0_word : std_logic_vector(31 downto 0);
    gpo1_gpo1_word : std_logic_vector(31 downto 0);
    gpo2_gpo2_word : std_logic_vector(31 downto 0);
    end record t_sfp_if_regs_master_out;
    subtype t_sfp_if_regs_slave_in is t_sfp_if_regs_master_out;
    type t_sfp_if_regs_slave_out is record
    gpi0_gpi0_word : std_logic_vector(31 downto 0);
    gpi1_gpi1_word : std_logic_vector(31 downto 0);
    gpi2_gpi2_word : std_logic_vector(31 downto 0);
    end record t_sfp_if_regs_slave_out;
    subtype t_sfp_if_regs_master_in is t_sfp_if_regs_slave_out;
    end sfp_ctrl_if_wb_pkg;
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use work.sfp_ctrl_if_wb_pkg.all;
    entity sfp_ctrl_if_wb is
    port (
    rst_n_i : in std_logic;
    clk_i : in std_logic;
    wb_cyc_i : in std_logic;
    wb_stb_i : in std_logic;
    wb_adr_i : in std_logic_vector(5 downto 2);
    wb_sel_i : in std_logic_vector(3 downto 0);
    wb_we_i : in std_logic;
    wb_dat_i : in std_logic_vector(31 downto 0);
    wb_ack_o : out std_logic;
    wb_err_o : out std_logic;
    wb_rty_o : out std_logic;
    wb_stall_o : out std_logic;
    wb_dat_o : out std_logic_vector(31 downto 0);
    -- Wires and registers
    sfp_if_regs_i : in t_sfp_if_regs_master_in;
    sfp_if_regs_o : out t_sfp_if_regs_master_out
    );
    end sfp_ctrl_if_wb;
    architecture syn of sfp_ctrl_if_wb is
    signal rd_req_int : std_logic;
    signal wr_req_int : std_logic;
    signal rd_ack_int : std_logic;
    signal wr_ack_int : std_logic;
    signal wb_en : std_logic;
    signal ack_int : std_logic;
    signal wb_rip : std_logic;
    signal wb_wip : std_logic;
    signal gpo0_gpo0_word_reg : std_logic_vector(31 downto 0);
    signal gpo0_wreq : std_logic;
    signal gpo0_wack : std_logic;
    signal gpo1_gpo1_word_reg : std_logic_vector(31 downto 0);
    signal gpo1_wreq : std_logic;
    signal gpo1_wack : std_logic;
    signal gpo2_gpo2_word_reg : std_logic_vector(31 downto 0);
    signal gpo2_wreq : std_logic;
    signal gpo2_wack : std_logic;
    signal rd_ack_d0 : std_logic;
    signal rd_dat_d0 : std_logic_vector(31 downto 0);
    signal wr_req_d0 : std_logic;
    signal wr_adr_d0 : std_logic_vector(5 downto 2);
    signal wr_dat_d0 : std_logic_vector(31 downto 0);
    begin
    -- WB decode signals
    wb_en <= wb_cyc_i and wb_stb_i;
    process (clk_i) begin
    if rising_edge(clk_i) then
    if rst_n_i = '0' then
    wb_rip <= '0';
    else
    wb_rip <= (wb_rip or (wb_en and not wb_we_i)) and not rd_ack_int;
    end if;
    end if;
    end process;
    rd_req_int <= (wb_en and not wb_we_i) and not wb_rip;
    process (clk_i) begin
    if rising_edge(clk_i) then
    if rst_n_i = '0' then
    wb_wip <= '0';
    else
    wb_wip <= (wb_wip or (wb_en and wb_we_i)) and not wr_ack_int;
    end if;
    end if;
    end process;
    wr_req_int <= (wb_en and wb_we_i) and not wb_wip;
    ack_int <= rd_ack_int or wr_ack_int;
    wb_ack_o <= ack_int;
    wb_stall_o <= not ack_int and wb_en;
    wb_rty_o <= '0';
    wb_err_o <= '0';
    -- pipelining for wr-in+rd-out
    process (clk_i) begin
    if rising_edge(clk_i) then
    if rst_n_i = '0' then
    rd_ack_int <= '0';
    wb_dat_o <= "00000000000000000000000000000000";
    wr_req_d0 <= '0';
    wr_adr_d0 <= "0000";
    wr_dat_d0 <= "00000000000000000000000000000000";
    else
    rd_ack_int <= rd_ack_d0;
    wb_dat_o <= rd_dat_d0;
    wr_req_d0 <= wr_req_int;
    wr_adr_d0 <= wb_adr_i;
    wr_dat_d0 <= wb_dat_i;
    end if;
    end if;
    end process;
    -- Register gpo0
    sfp_if_regs_o.gpo0_gpo0_word <= gpo0_gpo0_word_reg;
    process (clk_i) begin
    if rising_edge(clk_i) then
    if rst_n_i = '0' then
    gpo0_gpo0_word_reg <= "00000000000000000000000000000000";
    gpo0_wack <= '0';
    else
    if gpo0_wreq = '1' then
    gpo0_gpo0_word_reg <= wr_dat_d0;
    end if;
    gpo0_wack <= gpo0_wreq;
    end if;
    end if;
    end process;
    -- Register gpi0
    -- Register gpo1
    sfp_if_regs_o.gpo1_gpo1_word <= gpo1_gpo1_word_reg;
    process (clk_i) begin
    if rising_edge(clk_i) then
    if rst_n_i = '0' then
    gpo1_gpo1_word_reg <= "00000000000000000000000000000000";
    gpo1_wack <= '0';
    else
    if gpo1_wreq = '1' then
    gpo1_gpo1_word_reg <= wr_dat_d0;
    end if;
    gpo1_wack <= gpo1_wreq;
    end if;
    end if;
    end process;
    -- Register gpi1
    -- Register gpo2
    sfp_if_regs_o.gpo2_gpo2_word <= gpo2_gpo2_word_reg;
    process (clk_i) begin
    if rising_edge(clk_i) then
    if rst_n_i = '0' then
    gpo2_gpo2_word_reg <= "00000000000000000000000000000000";
    gpo2_wack <= '0';
    else
    if gpo2_wreq = '1' then
    gpo2_gpo2_word_reg <= wr_dat_d0;
    end if;
    gpo2_wack <= gpo2_wreq;
    end if;
    end if;
    end process;
    -- Register gpi2
    -- Process for write requests.
    process (wr_adr_d0, wr_req_d0, gpo0_wack, gpo1_wack, gpo2_wack) begin
    gpo0_wreq <= '0';
    gpo1_wreq <= '0';
    gpo2_wreq <= '0';
    case wr_adr_d0(5 downto 2) is
    when "1000" =>
    -- Reg gpo0
    gpo0_wreq <= wr_req_d0;
    wr_ack_int <= gpo0_wack;
    when "1001" =>
    -- Reg gpi0
    wr_ack_int <= wr_req_d0;
    when "1010" =>
    -- Reg gpo1
    gpo1_wreq <= wr_req_d0;
    wr_ack_int <= gpo1_wack;
    when "1011" =>
    -- Reg gpi1
    wr_ack_int <= wr_req_d0;
    when "1100" =>
    -- Reg gpo2
    gpo2_wreq <= wr_req_d0;
    wr_ack_int <= gpo2_wack;
    when "1101" =>
    -- Reg gpi2
    wr_ack_int <= wr_req_d0;
    when others =>
    wr_ack_int <= wr_req_d0;
    end case;
    end process;
    -- Process for read requests.
    process (wb_adr_i, rd_req_int, gpo0_gpo0_word_reg,
    sfp_if_regs_i.gpi0_gpi0_word, gpo1_gpo1_word_reg,
    sfp_if_regs_i.gpi1_gpi1_word, gpo2_gpo2_word_reg,
    sfp_if_regs_i.gpi2_gpi2_word) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    case wb_adr_i(5 downto 2) is
    when "1000" =>
    -- Reg gpo0
    rd_ack_d0 <= rd_req_int;
    rd_dat_d0 <= gpo0_gpo0_word_reg;
    when "1001" =>
    -- Reg gpi0
    rd_ack_d0 <= rd_req_int;
    rd_dat_d0 <= sfp_if_regs_i.gpi0_gpi0_word;
    when "1010" =>
    -- Reg gpo1
    rd_ack_d0 <= rd_req_int;
    rd_dat_d0 <= gpo1_gpo1_word_reg;
    when "1011" =>
    -- Reg gpi1
    rd_ack_d0 <= rd_req_int;
    rd_dat_d0 <= sfp_if_regs_i.gpi1_gpi1_word;
    when "1100" =>
    -- Reg gpo2
    rd_ack_d0 <= rd_req_int;
    rd_dat_d0 <= gpo2_gpo2_word_reg;
    when "1101" =>
    -- Reg gpi2
    rd_ack_d0 <= rd_req_int;
    rd_dat_d0 <= sfp_if_regs_i.gpi2_gpi2_word;
    when others =>
    rd_ack_d0 <= rd_req_int;
    end case;
    end process;
    end syn;
    modules/wr_sfp_ctrl/wr_sfp_ctrl.vhd 0 → 100644
    View file @ 3acd992e
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    library work;
    use work.wishbone_pkg.all;
    use work.sfp_ctrl_if_wb_pkg.all;
    entity wr_sfp_ctrl is
    generic
    (
    g_num_sfp : integer := 1 --number of sfp interfaces, max 24
    );
    port
    (
    clk_i : in std_logic;
    rst_n_i : in std_logic;
    --sfp i2c
    scl_pad_i : in std_logic_vector(g_num_sfp-1 downto 0);
    scl_pad_o : out std_logic_vector(g_num_sfp-1 downto 0);
    scl_padoen_o : out std_logic_vector(g_num_sfp-1 downto 0);
    sda_pad_i : in std_logic_vector(g_num_sfp-1 downto 0);
    sda_pad_o : out std_logic_vector(g_num_sfp-1 downto 0);
    sda_padoen_o : out std_logic_vector(g_num_sfp-1 downto 0);
    --sfp gpio
    detect_i : in std_logic_vector(g_num_sfp-1 downto 0);
    tx_fault_i : in std_logic_vector(g_num_sfp-1 downto 0);
    los_i : in std_logic_vector(g_num_sfp-1 downto 0);
    tx_diable_o : out std_logic_vector(g_num_sfp-1 downto 0);
    led_mode_o : out std_logic_vector(g_num_sfp-1 downto 0);
    led_synced_o : out std_logic_vector(g_num_sfp-1 downto 0);
    --wb
    wb_cyc_i : in std_logic;
    wb_stb_i : in std_logic;
    wb_adr_i : in std_logic_vector(31 downto 0);
    wb_sel_i : in std_logic_vector(3 downto 0);
    wb_we_i : in std_logic;
    wb_dat_i : in std_logic_vector(31 downto 0);
    wb_ack_o : out std_logic;
    wb_err_o : out std_logic;
    wb_rty_o : out std_logic;
    wb_stall_o : out std_logic;
    wb_dat_o : out std_logic_vector(31 downto 0)
    );
    end entity wr_sfp_ctrl;
    architecture rtl of wr_sfp_ctrl is
    function f_get_used_regs(num_sfp : integer) return integer is
    begin
    if(num_sfp <= 8 ) then
    return 1;
    elsif(num_sfp <= 16) then
    return 2;
    else
    return 3;
    end if;
    end function;
    constant c_MAX_PORTS : integer := 24;
    constant c_NUM_REGS : integer := f_get_used_regs(g_num_sfp);
    component sfp_ctrl_if_wb is
    port
    (
    rst_n_i : in std_logic;
    clk_i : in std_logic;
    wb_cyc_i : in std_logic;
    wb_stb_i : in std_logic;
    wb_adr_i : in std_logic_vector(5 downto 2);
    wb_sel_i : in std_logic_vector(3 downto 0);
    wb_we_i : in std_logic;
    wb_dat_i : in std_logic_vector(31 downto 0);
    wb_ack_o : out std_logic;
    wb_err_o : out std_logic;
    wb_rty_o : out std_logic;
    wb_stall_o : out std_logic;
    wb_dat_o : out std_logic_vector(31 downto 0);
    -- Wires and registers
    sfp_if_regs_i : in t_sfp_if_regs_master_in;
    sfp_if_regs_o : out t_sfp_if_regs_master_out
    );
    end component sfp_ctrl_if_wb;
    signal wb_regs_in : t_sfp_if_regs_master_in;
    signal wb_regs_out : t_sfp_if_regs_master_out;
    signal i2c_wb_dat_o : std_logic_vector(31 downto 0);
    signal i2c_wb_ack_o : std_logic;
    signal i2c_wb_stall_o : std_logic;
    signal i2c_wb_cyc_i : std_logic;
    signal sfp_wb_ack_o : std_logic;
    signal sfp_wb_err_o : std_logic;
    signal sfp_wb_rty_o : std_logic;
    signal sfp_wb_stall_o : std_logic;
    signal sfp_wb_dat_o : std_logic_vector(31 downto 0);
    signal sfp_wb_cyc_i : std_logic;
    begin
    U_i2c_master: wb_i2c_master
    generic map
    (
    g_interface_mode => CLASSIC,
    g_address_granularity => BYTE,
    g_num_interfaces => g_num_sfp
    )
    port map
    (
    clk_sys_i => clk_i,
    rst_n_i => rst_n_i,
    wb_adr_i => wb_adr_i(4 downto 0),
    wb_dat_i => wb_dat_i,
    wb_dat_o => i2c_wb_dat_o,
    wb_sel_i => wb_sel_i,
    wb_stb_i => wb_stb_i,
    wb_cyc_i => i2c_wb_cyc_i,
    wb_we_i => wb_we_i,
    wb_ack_o => i2c_wb_ack_o,
    wb_stall_o => i2c_wb_stall_o,
    int_o => open,
    scl_pad_i => scl_pad_i,
    scl_pad_o => scl_pad_o,
    scl_padoen_o => scl_padoen_o,
    sda_pad_i => sda_pad_i,
    sda_pad_o => sda_pad_o,
    sda_padoen_o => sda_padoen_o
    );
    --wb modules ack all addresses
    --mask cycles to each slave
    i2c_wb_cyc_i <= wb_cyc_i and not(wb_adr_i(5));
    sfp_wb_cyc_i <= wb_cyc_i and (wb_adr_i(5));
    U_wb_if: sfp_ctrl_if_wb
    port map
    (
    rst_n_i => rst_n_i,
    clk_i => clk_i,
    wb_cyc_i => wb_cyc_i,
    wb_stb_i => sfp_wb_cyc_i,
    wb_adr_i => wb_adr_i(5 downto 2),
    wb_sel_i => wb_sel_i(3 downto 0),
    wb_we_i => wb_we_i,
    wb_dat_i => wb_dat_i,
    wb_ack_o => sfp_wb_ack_o,
    wb_err_o => sfp_wb_err_o,
    wb_rty_o => sfp_wb_rty_o,
    wb_stall_o => sfp_wb_stall_o,
    wb_dat_o => sfp_wb_dat_o,
    -- Wires and registers
    sfp_if_regs_i => wb_regs_in,
    sfp_if_regs_o => wb_regs_out
    );
    --wb muxing
    wb_dat_o <= i2c_wb_dat_o when i2c_wb_ack_o = '1' else sfp_wb_dat_o;
    wb_ack_o <= i2c_wb_ack_o or sfp_wb_ack_o;
    wb_err_o <= sfp_wb_ack_o when sfp_wb_ack_o = '1' else '0';
    wb_rty_o <= sfp_wb_rty_o when sfp_wb_ack_o = '1' else '0';
    wb_stall_o <= sfp_wb_stall_o when sfp_wb_ack_o = '1' else '0';
    --register to port mapping
    gen_regs1: if c_NUM_REGS = 1 generate
    gen_regmap_0: for i in 0 to g_num_sfp-1 generate
    wb_regs_in.gpi0_gpi0_word((i*4)+3 downto (i*4)) <= '0' & los_i(i) & detect_i(i) & tx_fault_i(i);
    tx_diable_o(i) <= wb_regs_out.gpo0_gpo0_word((i*4));
    led_mode_o(i) <= wb_regs_out.gpo0_gpo0_word((i*4)+1);
    led_synced_o(i) <= wb_regs_out.gpo0_gpo0_word((i*4)+2);
    end generate;
    end generate;
    gen_regs2: if c_NUM_REGS = 2 generate
    gen_regmap_0: for i in 0 to 7 generate
    wb_regs_in.gpi0_gpi0_word((i*4)+3 downto (i*4)) <= '0' & los_i(i) & detect_i(i) & tx_fault_i(i);
    tx_diable_o(i) <= wb_regs_out.gpo0_gpo0_word((i*4));
    led_mode_o(i) <= wb_regs_out.gpo0_gpo0_word((i*4)+1);
    led_synced_o(i) <= wb_regs_out.gpo0_gpo0_word((i*4)+2);
    end generate;
    gen_regmap1: for i in 0 to g_num_sfp-8-1 generate
    wb_regs_in.gpi1_gpi1_word((i*4)+3 downto (i*4)) <= '0' & los_i(i+8) & detect_i(i+8) & tx_fault_i(i+8);
    tx_diable_o(i+8) <= wb_regs_out.gpo1_gpo1_word((i*4));
    led_mode_o(i+8) <= wb_regs_out.gpo1_gpo1_word((i*4)+1);
    led_synced_o(i+8) <= wb_regs_out.gpo1_gpo1_word((i*4)+2);
    end generate;
    end generate;
    gen_regs3: if c_NUM_REGS = 3 generate
    gen_regmap0: for i in 0 to 7 generate
    wb_regs_in.gpi0_gpi0_word((i*4)+3 downto (i*4)) <= '0' & los_i(i) & detect_i(i) & tx_fault_i(i);
    tx_diable_o(i) <= wb_regs_out.gpo0_gpo0_word((i*4));
    led_mode_o(i) <= wb_regs_out.gpo0_gpo0_word((i*4)+1);
    led_synced_o(i) <= wb_regs_out.gpo0_gpo0_word((i*4)+2);
    end generate;
    gen_regmap1: for i in 0 to 7 generate
    wb_regs_in.gpi1_gpi1_word((i*4)+3 downto (i*4)) <= '0' & los_i(i+8) & detect_i(i+8) & tx_fault_i(i+8);
    tx_diable_o(i+8) <= wb_regs_out.gpo1_gpo1_word((i*4));
    led_mode_o(i+8) <= wb_regs_out.gpo1_gpo1_word((i*4)+1);
    led_synced_o(i+8) <= wb_regs_out.gpo1_gpo1_word((i*4)+2);
    end generate;
    gen_regmap2: for i in 0 to g_num_sfp-16-1 generate
    wb_regs_in.gpi2_gpi2_word((i*4)+3 downto (i*4)) <= '0' & los_i(i+16) & detect_i(i+16) & tx_fault_i(i+16);
    tx_diable_o(i+16) <= wb_regs_out.gpo2_gpo2_word((i*4));
    led_mode_o(i+16) <= wb_regs_out.gpo2_gpo2_word((i*4)+1);
    led_synced_o(i+16) <= wb_regs_out.gpo2_gpo2_word((i*4)+2);
    end generate;
    end generate;
    end architecture;
    modules/wr_sfp_ctrl/xwr_sfp_ctrl.vhd 0 → 100644
    View file @ 3acd992e
    library ieee;
    use ieee.std_logic_1164.all;
    library work;
    use work.wishbone_pkg.all;
    entity xwr_sfp_ctrl is
    generic
    (
    g_num_sfp : integer := 1
    );
    port
    (
    clk_i : in std_logic;
    rst_n_i : in std_logic;
    --sfp i2c
    scl_pad_i : in std_logic_vector(g_num_sfp-1 downto 0);
    scl_pad_o : out std_logic_vector(g_num_sfp-1 downto 0);
    scl_padoen_o : out std_logic_vector(g_num_sfp-1 downto 0);
    sda_pad_i : in std_logic_vector(g_num_sfp-1 downto 0);
    sda_pad_o : out std_logic_vector(g_num_sfp-1 downto 0);
    sda_padoen_o : out std_logic_vector(g_num_sfp-1 downto 0);
    --sfp gpio
    detect_i : in std_logic_vector(g_num_sfp-1 downto 0);
    tx_fault_i : in std_logic_vector(g_num_sfp-1 downto 0);
    los_i : in std_logic_vector(g_num_sfp-1 downto 0);
    tx_diable_o : out std_logic_vector(g_num_sfp-1 downto 0);
    led_mode_o : out std_logic_vector(g_num_sfp-1 downto 0);
    led_synced_o : out std_logic_vector(g_num_sfp-1 downto 0);
    --wb
    slave_i : in t_wishbone_slave_in;
    slave_o : out t_wishbone_slave_out
    );
    end entity xwr_sfp_ctrl;
    architecture wrapper of xwr_sfp_ctrl is
    component wr_sfp_ctrl is
    generic
    (
    g_num_sfp : integer := 1
    );
    port
    (
    clk_i : in std_logic;
    rst_n_i : in std_logic;
    --sfp i2c
    scl_pad_i : in std_logic_vector(g_num_sfp-1 downto 0);
    scl_pad_o : out std_logic_vector(g_num_sfp-1 downto 0);
    scl_padoen_o : out std_logic_vector(g_num_sfp-1 downto 0);
    sda_pad_i : in std_logic_vector(g_num_sfp-1 downto 0);
    sda_pad_o : out std_logic_vector(g_num_sfp-1 downto 0);
    sda_padoen_o : out std_logic_vector(g_num_sfp-1 downto 0);
    --sfp gpio
    detect_i : in std_logic_vector(g_num_sfp-1 downto 0);
    tx_fault_i : in std_logic_vector(g_num_sfp-1 downto 0);
    los_i : in std_logic_vector(g_num_sfp-1 downto 0);
    tx_diable_o : out std_logic_vector(g_num_sfp-1 downto 0);
    led_mode_o : out std_logic_vector(g_num_sfp-1 downto 0);
    led_synced_o : out std_logic_vector(g_num_sfp-1 downto 0);
    --wb
    wb_cyc_i : in std_logic;
    wb_stb_i : in std_logic;
    wb_adr_i : in std_logic_vector(31 downto 0);
    wb_sel_i : in std_logic_vector(3 downto 0);
    wb_we_i : in std_logic;
    wb_dat_i : in std_logic_vector(31 downto 0);
    wb_ack_o : out std_logic;
    wb_err_o : out std_logic;
    wb_rty_o : out std_logic;
    wb_stall_o : out std_logic;
    wb_dat_o : out std_logic_vector(31 downto 0)
    );
    end component wr_sfp_ctrl;
    begin
    U_wrapped_wr_sfp_ctrl: wr_sfp_ctrl
    generic map
    (
    g_num_sfp => g_num_sfp
    )
    port map
    (
    clk_i => clk_i,
    rst_n_i => rst_n_i,
    scl_pad_i => scl_pad_i,
    scl_pad_o => scl_pad_o,
    scl_padoen_o => scl_padoen_o,
    sda_pad_i => sda_pad_i,
    sda_pad_o => sda_pad_o,
    sda_padoen_o => sda_padoen_o,
    detect_i => detect_i,
    tx_fault_i => tx_fault_i,
    los_i => los_i,
    tx_diable_o => tx_diable_o,
    led_mode_o => led_mode_o,
    led_synced_o => led_synced_o,
    wb_adr_i => slave_i.adr,
    wb_dat_i => slave_i.dat,
    wb_dat_o => slave_o.dat,
    wb_sel_i => slave_i.sel,
    wb_we_i => slave_i.we,
    wb_cyc_i => slave_i.cyc,
    wb_stb_i => slave_i.stb,
    wb_ack_o => slave_o.ack,
    wb_err_o => slave_o.err,
    wb_stall_o => slave_o.stall
    );
    end architecture;
    Markdown is supported
    0% or
    You are about to add 0 people to the discussion. Proceed with caution.
    Finish editing this message first!
    Please register or to comment