signal_agent function added to fix the invalid hierarchical access in riviera pro

304c8785 · CI · e26a8c8b · 304c8785 · 304c8785 · 304c8785
Commit 304c8785 authored Apr 13, 2022 by CI
4 changed files
--- a/testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
+++ b/testbench/wr_streamers/streamers-on-spec_trigger-distribution/main.sv
@@ -91,8 +91,8 @@ module main;
   

   // observe the link LEDs on both sides, and tell us when the link is ready.
-   wire link_up_a = SPEC_A.cmp_xwrc_board_spec.led_link_o;
-   wire link_up_b = SPEC_B.cmp_xwrc_board_spec.led_link_o;
+   wire link_up_a = $signal_agent("SPEC_A.cmp_xwrc_board_spec.led_link_o","led_link_o",1);
+   wire link_up_b = $signal_agent("SPEC_B.cmp_xwrc_board_spec.led_link_o","lend_link_o",1);

  initial begin
      // wait until both SPECs see the Ethernet link. Otherwise the packet we're going 

--- a/testbench/wr_streamers/streamers_multi_test/dataset.asdb
+++ b/testbench/wr_streamers/streamers_multi_test/dataset.asdb
--- a/testbench/wr_streamers/streamers_multi_test/library.cfg
+++ b/testbench/wr_streamers/streamers_multi_test/library.cfg
+$INCLUDE = "$VSIMSALIBRARYCFG"
+work = "./work/work.lib" 1649846817509
--- a/testbench/wr_streamers/streamers_multi_test/run_ci_riv.do
+++ b/testbench/wr_streamers/streamers_multi_test/run_ci_riv.do
-vsim -L unisim work.main -voptargs="+acc" -sv_seed random 
+vsim -L unisim work.main +access +r -voptargs="+acc" -sv_seed random 
 set StdArithNoWarnings 1
 set NumericStdNoWarnings 1
 do wave_ci.do
-run 10us
+run 20us
 wave zoomfull
 radix -hex
 quit