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White Rabbit core collection
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White Rabbit core collection
Commits
2e277e2a
Commit
2e277e2a
authored
Apr 27, 2012
by
Grzegorz Daniluk
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wr_core: enlarge RAM size to 80kB
parent
abeeb4fd
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3 changed files
with
4 additions
and
4 deletions
+4
-4
wr_core.vhd
modules/wrc_core/wr_core.vhd
+1
-1
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+1
-1
spec_top.vhd
top/spec_1_1/wr_core_demo/spec_top.vhd
+2
-2
No files found.
modules/wrc_core/wr_core.vhd
View file @
2e277e2a
...
...
@@ -67,7 +67,7 @@ entity wr_core is
g_rx_buffer_size
:
integer
:
=
1024
;
g_dpram_initf
:
string
:
=
""
;
g_dpram_initv
:
t_xwb_dpram_init
:
=
c_xwb_dpram_init_nothing
;
g_dpram_size
:
integer
:
=
16384
;
--in 32-bit words
g_dpram_size
:
integer
:
=
20480
;
--in 32-bit words
g_interface_mode
:
t_wishbone_interface_mode
:
=
PIPELINED
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
...
...
modules/wrc_core/xwr_core.vhd
View file @
2e277e2a
...
...
@@ -54,7 +54,7 @@ entity xwr_core is
g_ep_rxbuf_size
:
integer
:
=
1024
;
g_dpram_initf
:
string
:
=
""
;
g_dpram_initv
:
t_xwb_dpram_init
:
=
c_xwb_dpram_init_nothing
;
g_dpram_size
:
integer
:
=
16384
;
--in 32-bit words
g_dpram_size
:
integer
:
=
20480
;
--in 32-bit words
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
...
...
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @
2e277e2a
...
...
@@ -236,7 +236,7 @@ architecture rtl of spec_top is
g_aux_clks
:
integer
:
=
1
;
g_ep_rxbuf_size
:
integer
:
=
1024
;
g_dpram_initf
:
string
:
=
""
;
g_dpram_size
:
integer
:
=
16384
;
--in 32-bit words
g_dpram_size
:
integer
:
=
20480
;
--in 32-bit words
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
...
...
@@ -761,7 +761,7 @@ begin
g_aux_clks
=>
1
,
g_ep_rxbuf_size
=>
1024
,
g_dpram_initf
=>
""
,
g_dpram_size
=>
16384
,
g_dpram_size
=>
20480
,
--
16384,
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
WORD
)
port
map
(
...
...
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