Fix timing for SCU2 (except DDR)

28da1529 · Wesley W. Terpstra · 08abb2d3 · 28da1529 · 28da1529
Commit 28da1529 authored Jul 11, 2012 by Wesley W. Terpstra
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Showing with 16 additions and 10 deletions

scu_top.sdc top/gsi_scu2/wr_core_demo/scu_top.sdc +14 -8

scu_top.vhd top/gsi_scu2/wr_core_demo/scu_top.vhd +2 -2

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--- a/top/gsi_scu2/wr_core_demo/scu_top.sdc
+++ b/top/gsi_scu2/wr_core_demo/scu_top.sdc
 derive_pll_clocks -create_base_clocks
-
+create_clock -period 33Mhz -name LPC_FPGA_CLK [get_ports {LPC_FPGA_CLK}]
+create_clock -period 125Mhz -name pcie_refclk_i [get_ports {pcie_refclk_i}]
 derive_clock_uncertainty

-# connected to SOPC
-#create_clock -period 125Mhz -name F_PLL_6p [get_ports {F_PLL_6p}]
+# cut the clock domains from each other
+set_clock_groups -asynchronous \
+ -group { altera_reserved_tck                      } \
+ -group { clk_20m_vcxo_i       dmtd_clk_pll_inst|* } \
+ -group { clk_125m_pllref_p    sys_pll_inst|*      } \
+ -group { L_CLKp               ddr3_stub|*         } \
+ -group { pcie_refclk_i        PCIe|*              } \
+ -group {                      wr_gxb_phy*         } \
+ -group { LPC_FPGA_CLK                             }

-create_clock -period 125Mhz -name clk_125m_pllref_p [get_ports {clk_125m_pllref_p}]
-create_clock -period 125Mhz -name L_CLKp [get_ports {L_CLKp}]
-create_clock -period 125Mhz -name F_PLL_6p [get_ports {F_PLL_6p}]
-create_clock -period 20Mhz -name clk_20m_vcxo_i [get_ports {clk_20m_vcxo_i}]
-create_clock -period 33Mhz -name LPC_FPGA_CLK [get_ports {LPC_FPGA_CLK}]
\ No newline at end of file
+# these paths are supposedly made safe by Tom's sync_ffs. i have my doubts, but ...
+set_false_path -from {xwr_core:U_WR_CORE|wr_core:WRPC|xwr_pps_gen:PPS_GEN|wr_pps_gen:WRAPPED_PPSGEN|adj_utc*} \
+               -to   {xwr_core:U_WR_CORE|wr_core:WRPC|xwr_pps_gen:PPS_GEN|wr_pps_gen:WRAPPED_PPSGEN|cntr_utc*}
--- a/top/gsi_scu2/wr_core_demo/scu_top.vhd
+++ b/top/gsi_scu2/wr_core_demo/scu_top.vhd
@@ -76,7 +76,7 @@ entity scu_top is
    -----------------------------------------------------------------------
    -- AUX SFP 
    -----------------------------------------------------------------------
-    sfp1_tx_disable_o : out std_logic;
+    --sfp1_tx_disable_o : out std_logic;
    --sfp1_txp_o        : out std_logic;
    --sfp1_rxp_i        : in  std_logic;
    
@@ -355,7 +355,7 @@ begin
    c0     => pllout_clk_dmtd);         -- 62.5Mhz

  sys_pll_inst : sys_pll port map (
-    inclk0 => L_CLKp,                   -- 125Mhz 
+    inclk0 => clk_125m_pllref_p,        -- 125Mhz 
    c0     => pllout_clk_sys,           -- 62.5Mhy sys clk
    c1     => clk_reconf,               -- 50Mhz for reconfig block
    locked => open);