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White Rabbit core collection
Commits
26aea641
Commit
26aea641
authored
Dec 04, 2017
by
Grzegorz Daniluk
Browse files
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Merge branch 'greg-fasec' into proposed_master
parents
3ea2d74d
30363ccd
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Showing
10 changed files
with
3354 additions
and
3000 deletions
+3354
-3000
component.xml
board/fasec/component.xml
+3013
-2846
wr_fasec_pkg.vhd
board/fasec/wr_fasec_pkg.vhd
+16
-6
wrc_board_fasec.vhd
board/fasec/wrc_board_fasec.vhd
+40
-13
wrc_board_fasec_v4_1.tcl
board/fasec/wrc_board_fasec_v4_1.tcl
+136
-0
xwrc_board_fasec.vhd
board/fasec/xwrc_board_fasec.vhd
+30
-36
README.txt
syn/wrc_board_fasec_ip/README.txt
+3
-1
build.tcl
syn/wrc_board_fasec_ip/build.tcl
+3
-1
wrc_board_fasec_ip.tcl
syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl
+0
-2
fasec_ref_design.xdc
top/fasec_ref_design/fasec_ref_design.xdc
+14
-12
system_top.tcl
top/fasec_ref_design/system_top.tcl
+99
-83
No files found.
board/fasec/component.xml
View file @
26aea641
This diff is collapsed.
Click to expand it.
board/fasec/wr_fasec_pkg.vhd
View file @
26aea641
...
@@ -51,17 +51,27 @@ package wr_fasec_pkg is
...
@@ -51,17 +51,27 @@ package wr_fasec_pkg is
sfp_rxp_i
:
in
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_b
:
inout
std_logic
;
sfp_sda_i
:
in
std_logic
;
sfp_scl_b
:
inout
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_sda_t
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_scl_t
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
eeprom_scl_b
:
inout
std_logic
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_b
:
inout
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_sda_t
:
out
std_logic
;
thermo_id
:
inout
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
eeprom_scl_t
:
out
std_logic
;
thermo_id_i
:
in
std_logic
;
thermo_id_o
:
out
std_logic
;
thermo_id_t
:
out
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_rxd_i
:
in
std_logic
;
uart_txd_o
:
out
std_logic
;
uart_txd_o
:
out
std_logic
;
...
...
board/fasec/wrc_board_fasec.vhd
View file @
26aea641
...
@@ -7,7 +7,7 @@
...
@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Company : CERN (BE-CO-HT)
-- Created : 2017-08-02
-- Created : 2017-08-02
-- Last update: 2017-0
8-02
-- Last update: 2017-0
9-07
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- Description: Top-level wrapper for WR PTP core including all the modules
...
@@ -121,8 +121,12 @@ entity wrc_board_fasec is
...
@@ -121,8 +121,12 @@ entity wrc_board_fasec is
sfp_rx_p_i
:
in
std_logic
;
sfp_rx_p_i
:
in
std_logic
;
sfp_rx_n_i
:
in
std_logic
;
sfp_rx_n_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_b
:
inout
std_logic
;
sfp_sda_i
:
in
std_logic
;
sfp_scl_b
:
inout
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_sda_t
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_scl_t
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_tx_disable_o
:
out
std_logic
;
...
@@ -131,13 +135,19 @@ entity wrc_board_fasec is
...
@@ -131,13 +135,19 @@ entity wrc_board_fasec is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- I2C EEPROM
-- I2C EEPROM
---------------------------------------------------------------------------
---------------------------------------------------------------------------
eeprom_scl_b
:
inout
std_logic
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_b
:
inout
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_sda_t
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
eeprom_scl_t
:
out
std_logic
;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Onewire interface
-- Onewire interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
thermo_id
:
inout
std_logic
;
thermo_id_i
:
in
std_logic
;
thermo_id_o
:
out
std_logic
;
thermo_id_t
:
out
std_logic
;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- UART
-- UART
...
@@ -355,6 +365,10 @@ architecture std_wrapper of wrc_board_fasec is
...
@@ -355,6 +365,10 @@ architecture std_wrapper of wrc_board_fasec is
signal
wrs_tx_cfg_in
:
t_tx_streamer_cfg
;
signal
wrs_tx_cfg_in
:
t_tx_streamer_cfg
;
signal
wrs_rx_cfg_in
:
t_rx_streamer_cfg
;
signal
wrs_rx_cfg_in
:
t_rx_streamer_cfg
;
-- axi signals
signal
s_axi_araddr
:
std_logic_vector
(
31
downto
0
);
signal
s_axi_awaddr
:
std_logic_vector
(
31
downto
0
);
begin
-- architecture struct
begin
-- architecture struct
-- Map top-level signals to internal records
-- Map top-level signals to internal records
...
@@ -428,6 +442,9 @@ begin -- architecture struct
...
@@ -428,6 +442,9 @@ begin -- architecture struct
--wrs_rx_cfg_in.filter_remote <= wrs_rx_cfg_flt_r_i;
--wrs_rx_cfg_in.filter_remote <= wrs_rx_cfg_flt_r_i;
--wrs_rx_cfg_in.fixed_latency <= wrs_rx_cfg_fix_l_i;
--wrs_rx_cfg_in.fixed_latency <= wrs_rx_cfg_fix_l_i;
-- axi supports word-addressing only, i.e. per 4 bytes; shift for wb-bridge
s_axi_araddr
<=
"00"
&
s00_axi_araddr
(
31
downto
2
);
s_axi_awaddr
<=
"00"
&
s00_axi_awaddr
(
31
downto
2
);
-- Instantiate the records-based module
-- Instantiate the records-based module
cmp_xwrc_board_fasec
:
xwrc_board_fasec
cmp_xwrc_board_fasec
:
xwrc_board_fasec
generic
map
(
generic
map
(
...
@@ -468,17 +485,27 @@ begin -- architecture struct
...
@@ -468,17 +485,27 @@ begin -- architecture struct
sfp_rxp_i
=>
sfp_rx_p_i
,
sfp_rxp_i
=>
sfp_rx_p_i
,
sfp_rxn_i
=>
sfp_rx_n_i
,
sfp_rxn_i
=>
sfp_rx_n_i
,
sfp_det_i
=>
sfp_det_i
,
sfp_det_i
=>
sfp_det_i
,
sfp_sda_b
=>
sfp_sda_b
,
sfp_sda_i
=>
sfp_sda_i
,
sfp_scl_b
=>
sfp_scl_b
,
sfp_sda_o
=>
sfp_sda_o
,
sfp_sda_t
=>
sfp_sda_t
,
sfp_scl_i
=>
sfp_scl_i
,
sfp_scl_o
=>
sfp_scl_o
,
sfp_scl_t
=>
sfp_scl_t
,
sfp_rate_select_o
=>
sfp_rate_select_o
,
sfp_rate_select_o
=>
sfp_rate_select_o
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_los_i
=>
sfp_los_i
,
sfp_los_i
=>
sfp_los_i
,
--
--
eeprom_scl_b
=>
eeprom_scl_b
,
eeprom_sda_i
=>
eeprom_sda_i
,
eeprom_sda_b
=>
eeprom_sda_b
,
eeprom_sda_o
=>
eeprom_sda_o
,
eeprom_sda_t
=>
eeprom_sda_t
,
eeprom_scl_i
=>
eeprom_scl_i
,
eeprom_scl_o
=>
eeprom_scl_o
,
eeprom_scl_t
=>
eeprom_scl_t
,
--
--
thermo_id
=>
thermo_id
,
thermo_id_i
=>
thermo_id_i
,
thermo_id_o
=>
thermo_id_o
,
thermo_id_t
=>
thermo_id_t
,
--
--
uart_rxd_i
=>
uart_rxd_i
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
uart_txd_o
=>
uart_txd_o
,
...
@@ -493,7 +520,7 @@ begin -- architecture struct
...
@@ -493,7 +520,7 @@ begin -- architecture struct
--
--
s00_axi_aclk_o
=>
s00_axi_aclk_o
,
s00_axi_aclk_o
=>
s00_axi_aclk_o
,
s00_axi_aresetn
=>
s00_axi_aresetn
,
s00_axi_aresetn
=>
s00_axi_aresetn
,
s00_axi_awaddr
=>
s
00
_axi_awaddr
,
s00_axi_awaddr
=>
s_axi_awaddr
,
s00_axi_awprot
=>
(
others
=>
'0'
),
--s00_axi_awprot,
s00_axi_awprot
=>
(
others
=>
'0'
),
--s00_axi_awprot,
s00_axi_awvalid
=>
s00_axi_awvalid
,
s00_axi_awvalid
=>
s00_axi_awvalid
,
s00_axi_awready
=>
s00_axi_awready
,
s00_axi_awready
=>
s00_axi_awready
,
...
@@ -504,7 +531,7 @@ begin -- architecture struct
...
@@ -504,7 +531,7 @@ begin -- architecture struct
s00_axi_bresp
=>
s00_axi_bresp
,
s00_axi_bresp
=>
s00_axi_bresp
,
s00_axi_bvalid
=>
s00_axi_bvalid
,
s00_axi_bvalid
=>
s00_axi_bvalid
,
s00_axi_bready
=>
s00_axi_bready
,
s00_axi_bready
=>
s00_axi_bready
,
s00_axi_araddr
=>
s
00
_axi_araddr
,
s00_axi_araddr
=>
s_axi_araddr
,
s00_axi_arprot
=>
(
others
=>
'0'
),
--s00_axi_arprot,
s00_axi_arprot
=>
(
others
=>
'0'
),
--s00_axi_arprot,
s00_axi_arvalid
=>
s00_axi_arvalid
,
s00_axi_arvalid
=>
s00_axi_arvalid
,
s00_axi_arready
=>
s00_axi_arready
,
s00_axi_arready
=>
s00_axi_arready
,
...
...
board/fasec/wrc_board_fasec_v4_1.tcl
0 → 100644
View file @
26aea641
# Definitional proc to organize widgets for parameters.
proc
init_gui
{
IPINST
}
{
ipgui::add_param $IPINST -name
"Component_Name"
#Adding Page
ipgui::add_page $IPINST -name
"Page 0"
}
proc
update_PARAM_VALUE.g_aux_clks
{
PARAM_VALUE.g_aux_clks
}
{
# Procedure called to update g_aux_clks when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.g_aux_clks
{
PARAM_VALUE.g_aux_clks
}
{
# Procedure called to validate g_aux_clks
return true
}
proc
update_PARAM_VALUE.g_diag_id
{
PARAM_VALUE.g_diag_id
}
{
# Procedure called to update g_diag_id when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.g_diag_id
{
PARAM_VALUE.g_diag_id
}
{
# Procedure called to validate g_diag_id
return true
}
proc
update_PARAM_VALUE.g_diag_ro_vector_width
{
PARAM_VALUE.g_diag_ro_vector_width
}
{
# Procedure called to update g_diag_ro_vector_width when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.g_diag_ro_vector_width
{
PARAM_VALUE.g_diag_ro_vector_width
}
{
# Procedure called to validate g_diag_ro_vector_width
return true
}
proc
update_PARAM_VALUE.g_diag_rw_vector_width
{
PARAM_VALUE.g_diag_rw_vector_width
}
{
# Procedure called to update g_diag_rw_vector_width when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.g_diag_rw_vector_width
{
PARAM_VALUE.g_diag_rw_vector_width
}
{
# Procedure called to validate g_diag_rw_vector_width
return true
}
proc
update_PARAM_VALUE.g_diag_ver
{
PARAM_VALUE.g_diag_ver
}
{
# Procedure called to update g_diag_ver when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.g_diag_ver
{
PARAM_VALUE.g_diag_ver
}
{
# Procedure called to validate g_diag_ver
return true
}
proc
update_PARAM_VALUE.g_dpram_initf
{
PARAM_VALUE.g_dpram_initf
}
{
# Procedure called to update g_dpram_initf when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.g_dpram_initf
{
PARAM_VALUE.g_dpram_initf
}
{
# Procedure called to validate g_dpram_initf
return true
}
proc
update_PARAM_VALUE.g_fabric_iface
{
PARAM_VALUE.g_fabric_iface
}
{
# Procedure called to update g_fabric_iface when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.g_fabric_iface
{
PARAM_VALUE.g_fabric_iface
}
{
# Procedure called to validate g_fabric_iface
return true
}
proc
update_PARAM_VALUE.g_simulation
{
PARAM_VALUE.g_simulation
}
{
# Procedure called to update g_simulation when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.g_simulation
{
PARAM_VALUE.g_simulation
}
{
# Procedure called to validate g_simulation
return true
}
proc
update_PARAM_VALUE.g_with_external_clock_input
{
PARAM_VALUE.g_with_external_clock_input
}
{
# Procedure called to update g_with_external_clock_input when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.g_with_external_clock_input
{
PARAM_VALUE.g_with_external_clock_input
}
{
# Procedure called to validate g_with_external_clock_input
return true
}
proc
update_MODELPARAM_VALUE.g_simulation
{
MODELPARAM_VALUE.g_simulation PARAM_VALUE.g_simulation
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.g_simulation}
]
${MODELPARAM_VALUE.g_simulation}
}
proc
update_MODELPARAM_VALUE.g_with_external_clock_input
{
MODELPARAM_VALUE.g_with_external_clock_input PARAM_VALUE.g_with_external_clock_input
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.g_with_external_clock_input}
]
${MODELPARAM_VALUE.g_with_external_clock_input}
}
proc
update_MODELPARAM_VALUE.g_aux_clks
{
MODELPARAM_VALUE.g_aux_clks PARAM_VALUE.g_aux_clks
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.g_aux_clks}
]
${MODELPARAM_VALUE.g_aux_clks}
}
proc
update_MODELPARAM_VALUE.g_fabric_iface
{
MODELPARAM_VALUE.g_fabric_iface PARAM_VALUE.g_fabric_iface
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.g_fabric_iface}
]
${MODELPARAM_VALUE.g_fabric_iface}
}
proc
update_MODELPARAM_VALUE.g_dpram_initf
{
MODELPARAM_VALUE.g_dpram_initf PARAM_VALUE.g_dpram_initf
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.g_dpram_initf}
]
${MODELPARAM_VALUE.g_dpram_initf}
}
proc
update_MODELPARAM_VALUE.g_diag_id
{
MODELPARAM_VALUE.g_diag_id PARAM_VALUE.g_diag_id
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.g_diag_id}
]
${MODELPARAM_VALUE.g_diag_id}
}
proc
update_MODELPARAM_VALUE.g_diag_ver
{
MODELPARAM_VALUE.g_diag_ver PARAM_VALUE.g_diag_ver
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.g_diag_ver}
]
${MODELPARAM_VALUE.g_diag_ver}
}
proc
update_MODELPARAM_VALUE.g_diag_ro_vector_width
{
MODELPARAM_VALUE.g_diag_ro_vector_width PARAM_VALUE.g_diag_ro_vector_width
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.g_diag_ro_vector_width}
]
${MODELPARAM_VALUE.g_diag_ro_vector_width}
}
proc
update_MODELPARAM_VALUE.g_diag_rw_vector_width
{
MODELPARAM_VALUE.g_diag_rw_vector_width PARAM_VALUE.g_diag_rw_vector_width
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.g_diag_rw_vector_width}
]
${MODELPARAM_VALUE.g_diag_rw_vector_width}
}
board/fasec/xwrc_board_fasec.vhd
View file @
26aea641
...
@@ -125,8 +125,12 @@ entity xwrc_board_fasec is
...
@@ -125,8 +125,12 @@ entity xwrc_board_fasec is
sfp_rxp_i
:
in
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_det_i
:
in
std_logic
:
=
'1'
;
sfp_sda_b
:
inout
std_logic
;
sfp_sda_i
:
in
std_logic
;
sfp_scl_b
:
inout
std_logic
;
sfp_sda_o
:
out
std_logic
;
sfp_sda_t
:
out
std_logic
;
sfp_scl_i
:
in
std_logic
;
sfp_scl_o
:
out
std_logic
;
sfp_scl_t
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_tx_disable_o
:
out
std_logic
;
...
@@ -135,13 +139,19 @@ entity xwrc_board_fasec is
...
@@ -135,13 +139,19 @@ entity xwrc_board_fasec is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- I2C EEPROM
-- I2C EEPROM
---------------------------------------------------------------------------
---------------------------------------------------------------------------
eeprom_scl_b
:
inout
std_logic
;
eeprom_sda_i
:
in
std_logic
;
eeprom_sda_b
:
inout
std_logic
;
eeprom_sda_o
:
out
std_logic
;
eeprom_sda_t
:
out
std_logic
;
eeprom_scl_i
:
in
std_logic
;
eeprom_scl_o
:
out
std_logic
;
eeprom_scl_t
:
out
std_logic
;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Onewire interface
-- Onewire interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
thermo_id
:
inout
std_logic
;
thermo_id_i
:
in
std_logic
;
thermo_id_o
:
out
std_logic
;
thermo_id_t
:
out
std_logic
;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- UART
-- UART
...
@@ -307,18 +317,6 @@ architecture struct of xwrc_board_fasec is
...
@@ -307,18 +317,6 @@ architecture struct of xwrc_board_fasec is
signal
dac_dpll_load_p1
:
std_logic
;
signal
dac_dpll_load_p1
:
std_logic
;
signal
dac_dpll_data
:
std_logic_vector
(
15
downto
0
);
signal
dac_dpll_data
:
std_logic_vector
(
15
downto
0
);
-- EEPROM
signal
eeprom_sda_out
:
std_logic
;
signal
eeprom_sda_in
:
std_logic
;
signal
eeprom_scl_out
:
std_logic
;
signal
eeprom_scl_in
:
std_logic
;
-- SFP EEPROM
signal
sfp_sda_out
:
std_logic
;
signal
sfp_sda_in
:
std_logic
;
signal
sfp_scl_out
:
std_logic
;
signal
sfp_scl_in
:
std_logic
;
-- OneWire
-- OneWire
signal
onewire_in
:
std_logic_vector
(
1
downto
0
);
signal
onewire_in
:
std_logic_vector
(
1
downto
0
);
signal
onewire_en
:
std_logic_vector
(
1
downto
0
);
signal
onewire_en
:
std_logic_vector
(
1
downto
0
);
...
@@ -498,14 +496,14 @@ begin -- architecture struct
...
@@ -498,14 +496,14 @@ begin -- architecture struct
dac_dpll_data_o
=>
dac_dpll_data
,
dac_dpll_data_o
=>
dac_dpll_data
,
phy16_o
=>
phy16_from_wrc
,
phy16_o
=>
phy16_from_wrc
,
phy16_i
=>
phy16_to_wrc
,
phy16_i
=>
phy16_to_wrc
,
scl_o
=>
eeprom_scl_
ou
t
,
scl_o
=>
eeprom_scl_t
,
scl_i
=>
eeprom_scl_i
n
,
scl_i
=>
eeprom_scl_i
,
sda_o
=>
eeprom_sda_
ou
t
,
sda_o
=>
eeprom_sda_t
,
sda_i
=>
eeprom_sda_i
n
,
sda_i
=>
eeprom_sda_i
,
sfp_scl_o
=>
sfp_scl_
ou
t
,
sfp_scl_o
=>
sfp_scl_t
,
sfp_scl_i
=>
sfp_scl_i
n
,
sfp_scl_i
=>
sfp_scl_i
,
sfp_sda_o
=>
sfp_sda_
ou
t
,
sfp_sda_o
=>
sfp_sda_t
,
sfp_sda_i
=>
sfp_sda_i
n
,
sfp_sda_i
=>
sfp_sda_i
,
sfp_det_i
=>
sfp_det_i
,
sfp_det_i
=>
sfp_det_i
,
spi_sclk_o
=>
flash_sclk_o
,
spi_sclk_o
=>
flash_sclk_o
,
spi_ncs_o
=>
flash_ncs_o
,
spi_ncs_o
=>
flash_ncs_o
,
...
@@ -569,19 +567,15 @@ begin -- architecture struct
...
@@ -569,19 +567,15 @@ begin -- architecture struct
--onewire_in(0) <= onewire_i;
--onewire_in(0) <= onewire_i;
--onewire_in(1) <= '1';
--onewire_in(1) <= '1';
thermo_id
<=
'0'
when
onewire_en
(
0
)
=
'1'
else
'Z'
;
thermo_id_t
<=
'0'
when
onewire_en
(
0
)
=
'1'
else
'1'
;
onewire_in
(
0
)
<=
thermo_id
;
thermo_id_o
<=
'0'
;
onewire_in
(
0
)
<=
thermo_id_i
;
onewire_in
(
1
)
<=
'1'
;
onewire_in
(
1
)
<=
'1'
;
eeprom_scl_b
<=
'0'
when
eeprom_scl_out
=
'0'
else
'Z'
;
eeprom_sda_o
<=
'0'
;
eeprom_sda_b
<=
'0'
when
eeprom_sda_out
=
'0'
else
'Z'
;
eeprom_scl_o
<=
'0'
;
eeprom_scl_in
<=
eeprom_scl_b
;
sfp_sda_o
<=
'0'
;
eeprom_sda_in
<=
eeprom_sda_b
;
sfp_scl_o
<=
'0'
;
sfp_scl_b
<=
'0'
when
sfp_scl_out
=
'0'
else
'Z'
;
sfp_sda_b
<=
'0'
when
sfp_sda_out
=
'0'
else
'Z'
;
sfp_scl_in
<=
sfp_scl_b
;
sfp_sda_in
<=
sfp_sda_b
;
s00_axi_aclk_o
<=
clk_pll_62m5
;
s00_axi_aclk_o
<=
clk_pll_62m5
;
...
...
syn/wrc_board_fasec_ip/README.txt
View file @
26aea641
To create Vivado project for wrc_board_fasec IPcore generation, open Vivado and
To create Vivado project for wrc_board_fasec IPcore generation, open Vivado and
run build.tcl script.
run build.tcl script _before_ launching hdlmake; some files need copying in.
For instance:
vivado -mode batch -source build.tcl
syn/wrc_board_fasec_ip/build.tcl
View file @
26aea641
# Copy
component.xml
# Copy
some required files
file
copy -force ../../board/fasec/component.xml ../../.
file
copy -force ../../board/fasec/component.xml ../../.
file
mkdir ../../xgui
file
copy -force ../../board/fasec/wrc_board_fasec_v4_1.tcl ../../xgui/.
# Run tcl script generated by Vivado
# Run tcl script generated by Vivado
source
./wrc_board_fasec_ip.tcl
source
./wrc_board_fasec_ip.tcl
syn/wrc_board_fasec_ip/wrc_board_fasec_ip.tcl
View file @
26aea641
...
@@ -450,8 +450,6 @@ set_property "part" "xc7z030ffg676-2" $obj
...
@@ -450,8 +450,6 @@ set_property "part" "xc7z030ffg676-2" $obj
set_property
"sim.ip.auto_export_scripts"
"1"
$obj
set_property
"sim.ip.auto_export_scripts"
"1"
$obj
set_property
"simulator_language"
"Mixed"
$obj
set_property
"simulator_language"
"Mixed"
$obj
set_property
"target_language"
"VHDL"
$obj
set_property
"target_language"
"VHDL"
$obj
set_property
"xsim.array_display_limit"
"64"
$obj
set_property
"xsim.trace_limit"
"65536"
$obj
# Create 'sources_1' fileset (if not found
)
# Create 'sources_1' fileset (if not found
)
if
{[
string
equal
[
get_filesets -quiet sources_1
]
""
]}
{
if
{[
string
equal
[
get_filesets -quiet sources_1
]
""
]}
{
...
...
top/fasec_ref_design/fasec_ref_design.xdc
View file @
26aea641
...
@@ -20,25 +20,25 @@ set_property IOSTANDARD LVCMOS18 [get_ports pll25dac_cs_n_o]
...
@@ -20,25 +20,25 @@ set_property IOSTANDARD LVCMOS18 [get_ports pll25dac_cs_n_o]
set_property PACKAGE_PIN N7 [get_ports pll20dac_cs_n_o]
set_property PACKAGE_PIN N7 [get_ports pll20dac_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll20dac_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll20dac_cs_n_o]
set_property PACKAGE_PIN J14 [get_ports eeprom_
sda_b
]
set_property PACKAGE_PIN J14 [get_ports eeprom_
i2c_sda_io
]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_
sda_b
]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_
i2c_sda_io
]
set_property SLEW FAST [get_ports eeprom_
sda_b
]
set_property SLEW FAST [get_ports eeprom_
i2c_sda_io
]
set_property PACKAGE_PIN H14 [get_ports eeprom_
scl_b
]
set_property PACKAGE_PIN H14 [get_ports eeprom_
i2c_scl_io
]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_
scl_b
]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_
i2c_scl_io
]
set_property SLEW FAST [get_ports eeprom_
scl_b
]
set_property SLEW FAST [get_ports eeprom_
i2c_scl_io
]
set_property PACKAGE_PIN K10 [get_ports thermo_id]
set_property PACKAGE_PIN K10 [get_ports thermo_id
_tri_io
]
set_property IOSTANDARD LVCMOS18 [get_ports thermo_id]
set_property IOSTANDARD LVCMOS18 [get_ports thermo_id
_tri_io
]
set_property IOSTANDARD LVCMOS25 [get_ports
SFP_sda
]
set_property IOSTANDARD LVCMOS25 [get_ports
sfp_i2c_sda_io
]
set_property PACKAGE_PIN AB17 [get_ports
SFP_sda
]
set_property PACKAGE_PIN AB17 [get_ports
sfp_i2c_sda_io
]
set_property PACKAGE_PIN G16 [get_ports SFP_rx_los]
set_property PACKAGE_PIN G16 [get_ports SFP_rx_los]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_rx_los]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_rx_los]
set_property PACKAGE_PIN V4 [get_ports SFP_rxp]
set_property PACKAGE_PIN V4 [get_ports SFP_rxp]
set_property PACKAGE_PIN K15 [get_ports SFP_tx_fault]
set_property PACKAGE_PIN K15 [get_ports SFP_tx_fault]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_tx_fault]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_tx_fault]
set_property PACKAGE_PIN AB16 [get_ports
SFP_scl
]
set_property PACKAGE_PIN AB16 [get_ports
sfp_i2c_scl_io
]
set_property IOSTANDARD LVCMOS25 [get_ports
SFP_scl
]
set_property IOSTANDARD LVCMOS25 [get_ports
sfp_i2c_scl_io
]
set_property PACKAGE_PIN J15 [get_ports SFP_mod_abs]
set_property PACKAGE_PIN J15 [get_ports SFP_mod_abs]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_mod_abs]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_mod_abs]
set_property PACKAGE_PIN G14 [get_ports sfp_rate_select_o]
set_property PACKAGE_PIN G14 [get_ports sfp_rate_select_o]
...
@@ -70,3 +70,5 @@ set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n[2]}]
...
@@ -70,3 +70,5 @@ set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n[2]}]
set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks clk_sys]
set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks clk_sys]
top/fasec_ref_design/system_top.tcl
View file @
26aea641
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