added tx_prbs_sel, sfp_tx_disable, sfp_loss, sfp_tx_fault and full width…

added tx_prbs_sel, sfp_tx_disable, sfp_loss, sfp_tx_fault and full width loopback to MDIO Control register. Be careful: Single bit loopback was relocated to accomodate loopback(2:0)!

added tx_prbs_sel, sfp_tx_disable, sfp_loss, sfp_tx_fault and full width…
added tx_prbs_sel, sfp_tx_disable, sfp_loss, sfp_tx_fault and full width loopback to MDIO Control register. Be careful: Single bit loopback was relocated to accomodate loopback(2:0)!
25b049e4 · Peter Jansweijer · Grzegorz Daniluk · 419561be · 25b049e4 · 25b049e4
Commit 25b049e4 authored Jan 15, 2015 by Peter Jansweijer Committed by Grzegorz Daniluk Aug 03, 2015
12 changed files
--- a/modules/wr_endpoint/endpoint_pkg.vhd
+++ b/modules/wr_endpoint/endpoint_pkg.vhd
@@ -123,7 +123,11 @@ package endpoint_pkg is
      pps_csync_p1_i       : in  std_logic                     := '0';
      pps_valid_i          : in  std_logic                     := '1';
      phy_rst_o            : out std_logic;
-      phy_loopen_o         : out std_logic;
+      phy_loopen_o         : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in  std_logic;
+      phy_sfp_los_i        : in  std_logic;
+      phy_sfp_tx_disable_o : out std_logic;
      phy_enable_o         : out std_logic;
      phy_syncen_o         : out std_logic;
      phy_rdy_i            : in  std_logic;
@@ -221,7 +225,11 @@ package endpoint_pkg is
      pps_csync_p1_i       : in  std_logic;
      pps_valid_i          : in  std_logic                     := '1';
      phy_rst_o            : out std_logic;
-      phy_loopen_o         : out std_logic;
+      phy_loopen_o         : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in  std_logic;
+      phy_sfp_los_i        : in  std_logic;
+      phy_sfp_tx_disable_o : out std_logic;
      phy_enable_o         : out std_logic;
      phy_syncen_o         : out std_logic;
      phy_rdy_i            : in  std_logic;

--- a/modules/wr_endpoint/endpoint_private_pkg.vhd
+++ b/modules/wr_endpoint/endpoint_private_pkg.vhd
@@ -136,7 +136,11 @@ package endpoint_private_pkg is
      link_ctr_i                    : in  std_logic := '1';
      serdes_rst_o                  : out std_logic;
      serdes_syncen_o               : out std_logic;
-      serdes_loopen_o               : out std_logic;
+      serdes_loopen_o               : out std_logic_vector(2 downto 0);
+      serdes_tx_prbs_sel_o          : out std_logic_vector(2 downto 0);
+      serdes_sfp_tx_fault_i         : in  std_logic;
+      serdes_sfp_los_i              : in  std_logic;
+      serdes_sfp_tx_disable_o       : out std_logic;
      serdes_enable_o               : out std_logic;
      serdes_rdy_i                  : in  std_logic;
      serdes_tx_clk_i               : in  std_logic;
@@ -317,8 +321,12 @@ package endpoint_private_pkg is
      mdio_mcr_anrestart_o       : out std_logic;
      mdio_mcr_pdown_o           : out std_logic;
      mdio_mcr_anenable_o        : out std_logic;
-      mdio_mcr_loopback_o        : out std_logic;
      mdio_mcr_reset_o           : out std_logic;
+      mdio_mcr_loopback_o        : out std_logic_vector(2 downto 0);
+      mdio_mcr_sfp_tx_fault_i    : in  std_logic;
+      mdio_mcr_sfp_loss_i        : in  std_logic;
+      mdio_mcr_sfp_tx_disable_o  : out std_logic;
+      mdio_mcr_tx_prbs_sel_o     : out std_logic_vector(2 downto 0);
      mdio_msr_lstatus_i         : in  std_logic;
      lstat_read_notify_o        : out std_logic;
      mdio_msr_rfault_i          : in  std_logic;

--- a/modules/wr_endpoint/ep_1000basex_pcs.vhd
+++ b/modules/wr_endpoint/ep_1000basex_pcs.vhd
@@ -125,8 +125,20 @@ entity ep_1000basex_pcs is
    -- 1: serdes comma alignent is enabled.
    serdes_syncen_o : out std_logic;
-    -- 1: serdes near-end PMA loopback is enabled.
+    -- 000: loopback "normal operation" (see Serdes User Guide)
-    serdes_loopen_o : out std_logic;
+    serdes_loopen_o         : out std_logic_vector(2 downto 0);
+    -- 000: "normal operation" (see Serdes User Guide)
+    serdes_tx_prbs_sel_o    : out   std_logic_vector(2 downto 0);
+    -- 1: indicates laser fault
+    serdes_sfp_tx_fault_i   : in  std_logic;
+    -- 1: indicates Loss Of Signal
+    serdes_sfp_los_i        : in  std_logic;
+    -- 1: Disables the transmitter
+    serdes_sfp_tx_disable_o : out std_logic;
    -- 1: serdes TX/RX is enabled.
    serdes_enable_o : out std_logic;
@@ -196,7 +208,6 @@ architecture rtl of ep_1000basex_pcs is
  signal mdio_mcr_pdown           : std_logic;
  signal mdio_mcr_pdown_cpu       : std_logic;
  signal mdio_mcr_anenable        : std_logic;
-  signal mdio_mcr_loopback        : std_logic;
  signal mdio_mcr_reset           : std_logic;
  signal mdio_msr_lstatus         : std_logic;
  signal mdio_msr_rfault          : std_logic;
@@ -423,8 +434,12 @@ begin  -- rtl
      mdio_mcr_anrestart_o       => mdio_mcr_anrestart,
      mdio_mcr_pdown_o           => mdio_mcr_pdown_cpu,
      mdio_mcr_anenable_o        => mdio_mcr_anenable,
-      mdio_mcr_loopback_o        => mdio_mcr_loopback,
      mdio_mcr_reset_o           => mdio_mcr_reset,
+      mdio_mcr_loopback_o        => serdes_loopen_o,
+      mdio_mcr_sfp_tx_fault_i    => serdes_sfp_tx_fault_i,
+      mdio_mcr_sfp_loss_i        => serdes_sfp_los_i,
+      mdio_mcr_sfp_tx_disable_o  => serdes_sfp_tx_disable_o,
+      mdio_mcr_tx_prbs_sel_o     => serdes_tx_prbs_sel_o,
      mdio_msr_lstatus_i         => mdio_msr_lstatus,
      mdio_msr_rfault_i          => mdio_msr_rfault,
      mdio_msr_anegcomplete_i    => mdio_msr_anegcomplete,
@@ -519,8 +534,6 @@ begin  -- rtl
  link_ok_o <= link_ok and synced;
-  serdes_loopen_o <= mdio_mcr_loopback;
  --RMON events
  U_sync_tx_underrun: gc_sync_ffs
  generic map (

--- a/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+++ b/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ep_pcs_tbi_mdio_wb.vhd
 -- Author         : auto-generated by wbgen2 from pcs_regs.wb
-- Created        : Thu Aug  1 10:24:16 2013
+-- Created        : 01/15/15 14:37:10
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
@@ -37,10 +37,18 @@ entity ep_pcs_tbi_mdio_wb is
    mdio_mcr_pdown_o                         : out    std_logic;
 -- Port for BIT field: 'Auto-Negotiation Enable' in reg: 'MDIO Control Register'
    mdio_mcr_anenable_o                      : out    std_logic;
-- Port for BIT field: 'Loopback' in reg: 'MDIO Control Register'
-    mdio_mcr_loopback_o                      : out    std_logic;
 -- Port for MONOSTABLE field: 'Reset' in reg: 'MDIO Control Register'
    mdio_mcr_reset_o                         : out    std_logic;
+-- Port for std_logic_vector field: 'Loopback' in reg: 'MDIO Control Register'
+    mdio_mcr_loopback_o                      : out    std_logic_vector(2 downto 0);
+-- Port for BIT field: 'SFP TX Fault Status' in reg: 'MDIO Control Register'
+    mdio_mcr_sfp_tx_fault_i                  : in     std_logic;
+-- Port for BIT field: 'SFP LOS' in reg: 'MDIO Control Register'
+    mdio_mcr_sfp_loss_i                      : in     std_logic;
+-- Port for BIT field: 'SFP TX Disable' in reg: 'MDIO Control Register'
+    mdio_mcr_sfp_tx_disable_o                : out    std_logic;
+-- Port for std_logic_vector field: 'tx_prbs_sel' in reg: 'MDIO Control Register'
+    mdio_mcr_tx_prbs_sel_o                   : out    std_logic_vector(2 downto 0);
 -- Port for BIT field: 'Link Status' in reg: 'MDIO Status Register'
    mdio_msr_lstatus_i                       : in     std_logic;
    lstat_read_notify_o                      : out    std_logic;
@@ -82,9 +90,11 @@ signal mdio_mcr_anrestart_dly0                  : std_logic      ;
 signal mdio_mcr_anrestart_int                   : std_logic      ;
 signal mdio_mcr_pdown_int                       : std_logic      ;
 signal mdio_mcr_anenable_int                    : std_logic      ;
-signal mdio_mcr_loopback_int                    : std_logic      ;
 signal mdio_mcr_reset_dly0                      : std_logic      ;
 signal mdio_mcr_reset_int                       : std_logic      ;
+signal mdio_mcr_loopback_int                    : std_logic_vector(2 downto 0);
+signal mdio_mcr_sfp_tx_disable_int              : std_logic      ;
+signal mdio_mcr_tx_prbs_sel_int                 : std_logic_vector(2 downto 0);
 signal mdio_advertise_pause_int                 : std_logic_vector(1 downto 0);
 signal mdio_advertise_rfault_int                : std_logic_vector(1 downto 0);
 signal mdio_wr_spec_tx_cal_int                  : std_logic      ;
@@ -135,8 +145,10 @@ begin
      mdio_mcr_anrestart_int <= '0';
      mdio_mcr_pdown_int <= '0';
      mdio_mcr_anenable_int <= '0';
-      mdio_mcr_loopback_int <= '0';
      mdio_mcr_reset_int <= '0';
+      mdio_mcr_loopback_int <= "000";
+      mdio_mcr_sfp_tx_disable_int <= '0';
+      mdio_mcr_tx_prbs_sel_int <= "000";
      lstat_read_notify_o <= '0';
      mdio_advertise_pause_int <= "00";
      mdio_advertise_rfault_int <= "00";
@@ -175,8 +187,10 @@ begin
              mdio_mcr_anrestart_int <= wrdata_reg(9);
              mdio_mcr_pdown_int <= wrdata_reg(11);
              mdio_mcr_anenable_int <= wrdata_reg(12);
-              mdio_mcr_loopback_int <= wrdata_reg(14);
              mdio_mcr_reset_int <= wrdata_reg(15);
+              mdio_mcr_loopback_int <= wrdata_reg(18 downto 16);
+              mdio_mcr_sfp_tx_disable_int <= wrdata_reg(21);
+              mdio_mcr_tx_prbs_sel_int <= wrdata_reg(24 downto 22);
            end if;
            rddata_reg(4 downto 0) <= "00000";
            rddata_reg(5) <= mdio_mcr_uni_en_int;
@@ -188,17 +202,13 @@ begin
            rddata_reg(11) <= mdio_mcr_pdown_int;
            rddata_reg(12) <= mdio_mcr_anenable_int;
            rddata_reg(13) <= '0';
-            rddata_reg(14) <= mdio_mcr_loopback_int;
+            rddata_reg(14) <= '0';
            rddata_reg(15) <= '0';
-            rddata_reg(16) <= 'X';
+            rddata_reg(18 downto 16) <= mdio_mcr_loopback_int;
-            rddata_reg(17) <= 'X';
+            rddata_reg(19) <= mdio_mcr_sfp_tx_fault_i;
-            rddata_reg(18) <= 'X';
+            rddata_reg(20) <= mdio_mcr_sfp_loss_i;
-            rddata_reg(19) <= 'X';
+            rddata_reg(21) <= mdio_mcr_sfp_tx_disable_int;
-            rddata_reg(20) <= 'X';
+            rddata_reg(24 downto 22) <= mdio_mcr_tx_prbs_sel_int;
-            rddata_reg(21) <= 'X';
-            rddata_reg(22) <= 'X';
-            rddata_reg(23) <= 'X';
-            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
@@ -475,8 +485,6 @@ begin
  mdio_mcr_pdown_o <= mdio_mcr_pdown_int;
 -- Auto-Negotiation Enable
  mdio_mcr_anenable_o <= mdio_mcr_anenable_int;
-- Loopback
-  mdio_mcr_loopback_o <= mdio_mcr_loopback_int;
 -- Reset
  process (clk_sys_i, rst_n_i)
  begin
@@ -490,6 +498,14 @@ begin
  end process;
+-- Loopback
+  mdio_mcr_loopback_o <= mdio_mcr_loopback_int;
+-- SFP TX Fault Status
+-- SFP LOS
+-- SFP TX Disable
+  mdio_mcr_sfp_tx_disable_o <= mdio_mcr_sfp_tx_disable_int;
+-- tx_prbs_sel
+  mdio_mcr_tx_prbs_sel_o <= mdio_mcr_tx_prbs_sel_int;
 -- Link Status
 -- Remote Fault
 -- Auto-Negotiation Complete

--- a/modules/wr_endpoint/pcs_regs.wb
+++ b/modules/wr_endpoint/pcs_regs.wb
@@ -152,16 +152,12 @@ peripheral {
 			};
 			field {
-				 name = "Loopback";
+				 name = "Reserved";
-				 description = "1 = enable loopback mode \
+				 description = "Always return 0s, writes ignored.";
-				 0 = disable loopback mode \
+				 prefix = "RESV";
-				 With the TBI version, loopback bit is connected to PHY loopback enable pin. When set to 1, indicates to the external PHY to enter loopback mode";
+				 type = CONSTANT;
+				 size = 1;
-				 prefix = "loopback";
+				 value = 0;
-				 align = 14;
-				 type = BIT;
-				 access_bus = READ_WRITE;
-				 access_dev = READ_ONLY;
 			};
 			field {
@@ -174,6 +170,68 @@ peripheral {
 				 prefix = "reset";
 				 type = MONOSTABLE;
 			};
+			field {
+				 name = "Loopback";
+				 description = "100 = far end loopback mode \
+				 000 = normal mode \
+				 See also Transceiver documentation (for example Xilinx UG476 Table 2-37 and Figure 2-23";
+				 prefix = "loopback";
+				 align = 16;
+ 				 size = 3;
+         value = 0;
+				 type = SLV;
+				 access_bus = READ_WRITE;
+ 				 access_dev = READ_ONLY;
+			};
+			field {
+				 name = "SFP TX Fault Status";
+				 description = "1 = Some kind of laser failure\
+				 0 = SFP Laser okay";
+				 prefix = "sfp_tx_fault";
+				 type = BIT;
+				 access_bus=READ_ONLY;
+				 access_dev=WRITE_ONLY;
+			};
+			field {
+				 name = "SFP LOS";
+				 description = "1 = Loss of signal\
+				 0 = SFP Receiver signal strength okay";
+				 prefix = "sfp_loss";
+				 type = BIT;
+				 access_bus=READ_ONLY;
+				 access_dev=WRITE_ONLY;
+			};
+			field {
+				 name = "SFP TX Disable";
+				 description = "Disables the SFP Transmitter \
+				                1 = SFP TX Disabled\
+				                0 = SFP TX Enabled";
+				 prefix = "sfp_tx_disable";
+				 type = BIT;
+         value = 0;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+			};
+			field {
+				 name = "tx_prbs_sel";
+				 description = "PRBS selection \
+				                000 = Normal mode\
+				                0010 = PRBS-7";
+				 prefix = "tx_prbs_sel";
+				 align = 22;
+ 				 size = 3;
+         value = 0;
+				 type = SLV;
+				 access_bus = READ_WRITE;
+ 				 access_dev = READ_ONLY;
+			};
 	 };

--- a/modules/wr_endpoint/wr_endpoint.vhd
+++ b/modules/wr_endpoint/wr_endpoint.vhd
@@ -106,7 +106,11 @@ entity wr_endpoint is
 -------------------------------------------------------------------------------    
    phy_rst_o    : out std_logic;
-    phy_loopen_o : out std_logic;
+    phy_loopen_o         : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in  std_logic;
+    phy_sfp_los_i        : in  std_logic;
+    phy_sfp_tx_disable_o : out std_logic;
    phy_enable_o : out std_logic;
    phy_syncen_o : out std_logic;
    phy_rdy_i    : in  std_logic;
@@ -515,6 +519,10 @@ begin
      serdes_rst_o    => phy_rst_o,
      serdes_loopen_o => phy_loopen_o,
+      serdes_tx_prbs_sel_o     => phy_tx_prbs_sel_o,
+      serdes_sfp_tx_fault_i    => phy_sfp_tx_fault_i,
+      serdes_sfp_los_i         => phy_sfp_los_i,
+      serdes_sfp_tx_disable_o  => phy_sfp_tx_disable_o,
      serdes_enable_o => phy_enable_o,
      serdes_syncen_o => phy_syncen_o,
      serdes_rdy_i    => phy_rdy_i,

--- a/modules/wr_endpoint/xwr_endpoint.vhd
+++ b/modules/wr_endpoint/xwr_endpoint.vhd
@@ -95,7 +95,11 @@ entity xwr_endpoint is
 -------------------------------------------------------------------------------    
    phy_rst_o    : out std_logic;
-    phy_loopen_o : out std_logic;
+    phy_loopen_o         : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in std_logic;
+    phy_sfp_los_i        : in std_logic;
+    phy_sfp_tx_disable_o : out std_logic;
    phy_enable_o : out std_logic;
    phy_syncen_o : out std_logic;
    phy_rdy_i    : in  std_logic;
@@ -291,6 +295,10 @@ begin
      pps_valid_i          => pps_valid_i,
      phy_rst_o            => phy_rst_o,
      phy_loopen_o         => phy_loopen_o,
+      phy_tx_prbs_sel_o    => phy_tx_prbs_sel_o,
+      phy_sfp_tx_fault_i   => phy_sfp_tx_fault_i,
+      phy_sfp_los_i        => phy_sfp_los_i,
+      phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
      phy_enable_o         => phy_enable_o,
      phy_syncen_o         => phy_syncen_o,
      phy_rdy_i            => phy_rdy_i,

--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -151,9 +151,13 @@ entity wr_core is
    phy_rx_enc_err_i  : in std_logic;
    phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
-    phy_rst_o    : out std_logic;
+    phy_rst_o            : out std_logic;
-    phy_loopen_o : out std_logic;
+    phy_rdy_i            : in  std_logic := '1';
-    phy_rdy_i    : in  std_logic := '1';
+    phy_loopen_o         : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in std_logic := '0';
+    phy_sfp_los_i        : in std_logic := '0';
+    phy_sfp_tx_disable_o : out std_logic;
    -----------------------------------------
    --GPIO
@@ -649,19 +653,23 @@ begin
      pps_csync_p1_i => s_pps_csync,
      pps_valid_i    => pps_valid,
-      phy_rst_o          => phy_rst_o,
+      phy_rst_o            => phy_rst_o,
-      phy_loopen_o       => phy_loopen_o,
+      phy_rdy_i            => phy_rdy_i,
-      phy_rdy_i          => phy_rdy_i,
+      phy_loopen_o         => phy_loopen_o,
-      phy_ref_clk_i      => phy_ref_clk_i,
+      phy_tx_prbs_sel_o    => phy_tx_prbs_sel_o,
-      phy_tx_data_o      => phy_tx_data_int,
+      phy_sfp_tx_fault_i   => phy_sfp_tx_fault_i,
-      phy_tx_k_o         => phy_tx_k_int,
+      phy_sfp_los_i        => phy_sfp_los_i,
-      phy_tx_disparity_i => phy_tx_disparity_i,
+      phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
-      phy_tx_enc_err_i   => phy_tx_enc_err_i,
+      phy_ref_clk_i        => phy_ref_clk_i,
-      phy_rx_data_i      => phy_rx_data_int,
+      phy_tx_data_o        => phy_tx_data_int,
-      phy_rx_clk_i       => phy_rx_rbclk_i,
+      phy_tx_k_o           => phy_tx_k_int,
-      phy_rx_k_i         => phy_rx_k_int,
+      phy_tx_disparity_i   => phy_tx_disparity_i,
-      phy_rx_enc_err_i   => phy_rx_enc_err_i,
+      phy_tx_enc_err_i     => phy_tx_enc_err_i,
-      phy_rx_bitslide_i  => phy_rx_bitslide_int,
+      phy_rx_data_i        => phy_rx_data_int,
+      phy_rx_clk_i         => phy_rx_rbclk_i,
+      phy_rx_k_i           => phy_rx_k_int,
+      phy_rx_enc_err_i     => phy_rx_enc_err_i,
+      phy_rx_bitslide_i    => phy_rx_bitslide_int,
      src_o => ep_src_out,
      src_i => ep_src_in,

--- a/modules/wrc_core/wrcore_pkg.vhd
+++ b/modules/wrc_core/wrcore_pkg.vhd
@@ -323,26 +323,30 @@ package wrcore_pkg is
      pps_ext_i  : in std_logic                               := '0';
      rst_n_i    : in std_logic;
-      dac_hpll_load_p1_o : out std_logic;
+      dac_hpll_load_p1_o   : out std_logic;
-      dac_hpll_data_o    : out std_logic_vector(15 downto 0);
+      dac_hpll_data_o      : out std_logic_vector(15 downto 0);
-      dac_dpll_load_p1_o : out std_logic;
+      dac_dpll_load_p1_o   : out std_logic;
-      dac_dpll_data_o    : out std_logic_vector(15 downto 0);
+      dac_dpll_data_o      : out std_logic_vector(15 downto 0);
-      phy_ref_clk_i      : in  std_logic                    := '0';
+      phy_ref_clk_i        : in  std_logic                    := '0';
-      phy_tx_data_o      : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+      phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
-      phy_tx_k_o         : out std_logic;
+      phy_tx_k_o           : out std_logic;
-      phy_tx_k16_o       : out std_logic;
+      phy_tx_k16_o         : out std_logic;
-      phy_tx_disparity_i : in  std_logic                    := '0';
+      phy_tx_disparity_i   : in  std_logic                    := '0';
-      phy_tx_enc_err_i   : in  std_logic                    := '0';
+      phy_tx_enc_err_i     : in  std_logic                    := '0';
-      phy_rx_data_i      : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_data_i        : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
-      phy_rx_rbclk_i     : in  std_logic                    := '0';
+      phy_rx_rbclk_i       : in  std_logic                    := '0';
-      phy_rx_k_i         : in  std_logic                    := '0';
+      phy_rx_k_i           : in  std_logic                    := '0';
-      phy_rx_k16_i       : in std_logic                     := '0';
+      phy_rx_k16_i         : in std_logic                     := '0';
-      phy_rx_enc_err_i   : in  std_logic                    := '0';
+      phy_rx_enc_err_i     : in  std_logic                    := '0';
-      phy_rx_bitslide_i  : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
+      phy_rx_bitslide_i    : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
-      phy_rst_o          : out std_logic;
+      phy_rst_o            : out std_logic;
-      phy_loopen_o       : out std_logic;
+      phy_rdy_i            : in  std_logic := '1';
-      phy_rdy_i          : in  std_logic := '1';
+      phy_loopen_o         : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in std_logic := '0';
+      phy_sfp_los_i        : in std_logic := '0';
+      phy_sfp_tx_disable_o : out std_logic;
      led_act_o  : out std_logic;
      led_link_o : out std_logic;
@@ -475,8 +479,12 @@ package wrcore_pkg is
      phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
      phy_rst_o    : out std_logic;
-      phy_loopen_o : out std_logic;
      phy_rdy_i    : in  std_logic := '1';
+      phy_loopen_o         : out std_logic_vector(2 downto 0);
+      phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+      phy_sfp_tx_fault_i   : in std_logic := '0';
+      phy_sfp_los_i        : in std_logic := '0';
+      phy_sfp_tx_disable_o : out std_logic;
      -----------------------------------------
      --GPIO

--- a/modules/wrc_core/xwr_core.vhd
+++ b/modules/wrc_core/xwr_core.vhd
@@ -122,23 +122,27 @@ entity xwr_core is
    -- PHY I/f
    phy_ref_clk_i : in std_logic;
-    phy_tx_data_o      : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_tx_data_o        : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
-    phy_tx_k_o         : out std_logic;
+    phy_tx_k_o           : out std_logic;
-    phy_tx_k16_o       : out std_logic;
+    phy_tx_k16_o         : out std_logic;
-    phy_tx_disparity_i : in  std_logic;
+    phy_tx_disparity_i   : in  std_logic;
-    phy_tx_enc_err_i   : in  std_logic;
+    phy_tx_enc_err_i     : in  std_logic;
-    phy_rx_data_i     : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_data_i        : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
-    phy_rx_rbclk_i    : in std_logic;
+    phy_rx_rbclk_i       : in std_logic;
-    phy_rx_k_i        : in std_logic;
+    phy_rx_k_i           : in std_logic;
-    phy_rx_k16_i      : in std_logic;
+    phy_rx_k16_i         : in std_logic;
-    phy_rx_enc_err_i  : in std_logic;
+    phy_rx_enc_err_i     : in std_logic;
-    phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
+    phy_rx_bitslide_i    : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
-    phy_rst_o    : out std_logic;
+    phy_rst_o            : out std_logic;
-    phy_loopen_o : out std_logic;
+    phy_rdy_i            : in  std_logic := '1';
-    phy_rdy_i    : in  std_logic := '1';
+    phy_loopen_o         : out std_logic_vector(2 downto 0);
+    phy_tx_prbs_sel_o    : out std_logic_vector(2 downto 0);
+    phy_sfp_tx_fault_i   : in std_logic := '0';
+    phy_sfp_los_i        : in std_logic := '0';
+    phy_sfp_tx_disable_o : out std_logic;
    -----------------------------------------
    --GPIO
    -----------------------------------------
@@ -254,24 +258,30 @@ begin
      pps_ext_i     => pps_ext_i,
      rst_n_i       => rst_n_i,
-      dac_hpll_load_p1_o => dac_hpll_load_p1_o,
+      dac_hpll_load_p1_o   => dac_hpll_load_p1_o,
-      dac_hpll_data_o    => dac_hpll_data_o,
+      dac_hpll_data_o      => dac_hpll_data_o,
-      dac_dpll_load_p1_o => dac_dpll_load_p1_o,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1_o,
-      dac_dpll_data_o    => dac_dpll_data_o,
+      dac_dpll_data_o      => dac_dpll_data_o,
-      phy_ref_clk_i      => phy_ref_clk_i,
+      phy_ref_clk_i        => phy_ref_clk_i,
-      phy_tx_data_o      => phy_tx_data_o,
+      phy_tx_data_o        => phy_tx_data_o,
-      phy_tx_k_o         => phy_tx_k_o,
+      phy_tx_k_o           => phy_tx_k_o,
-      phy_tx_disparity_i => phy_tx_disparity_i,
+      phy_tx_k16_o         => phy_tx_k16_o,
-      phy_tx_enc_err_i   => phy_tx_enc_err_i,
+      phy_tx_disparity_i   => phy_tx_disparity_i,
-      phy_rx_data_i      => phy_rx_data_i,
+      phy_tx_enc_err_i     => phy_tx_enc_err_i,
-      phy_rx_rbclk_i     => phy_rx_rbclk_i,
+      phy_rx_data_i        => phy_rx_data_i,
-      phy_rx_k_i         => phy_rx_k_i,
+      phy_rx_rbclk_i       => phy_rx_rbclk_i,
-      phy_rx_enc_err_i   => phy_rx_enc_err_i,
+      phy_rx_k_i           => phy_rx_k_i,
-      phy_rx_bitslide_i  => phy_rx_bitslide_i,
+      phy_rx_k16_i         => phy_rx_k16_i,
-      phy_rst_o          => phy_rst_o,
+      phy_rx_enc_err_i     => phy_rx_enc_err_i,
-      phy_loopen_o       => phy_loopen_o,
+      phy_rx_bitslide_i    => phy_rx_bitslide_i,
-      phy_rdy_i          => phy_rdy_i,
+      phy_rst_o            => phy_rst_o,
+      phy_rdy_i            => phy_rdy_i,
+      phy_loopen_o         => phy_loopen_o,
+      phy_tx_prbs_sel_o    => phy_tx_prbs_sel_o,
+      phy_sfp_tx_fault_i   => phy_sfp_tx_fault_i,
+      phy_sfp_los_i        => phy_sfp_los_i,
+      phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
      led_act_o  => led_act_o,
      led_link_o => led_link_o,

--- a/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
+++ b/platform/xilinx/wr_gtp_phy/whiterabbit_gtxe2_channel_wrapper_gt.vhd
@@ -155,8 +155,9 @@ port
    --------------------- Transmit Ports - TX Gearbox Ports --------------------
    TXCHARISK_IN                            : in   std_logic_vector(1 downto 0);
    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
-    TXRESETDONE_OUT                         : out  std_logic
+    TXRESETDONE_OUT                         : out  std_logic;
+    ------------------ Transmit Ports - pattern Generator Ports ----------------
+    TXPRBSSEL_IN                            : in   std_logic_vector(2 downto 0)
 );
@@ -789,7 +790,7 @@ begin
        ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
        TX8B10BBYPASS                   =>      tied_to_ground_vec_i(7 downto 0),
        ------------------ Transmit Ports - pattern Generator Ports ----------------
-        TXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        TXPRBSSEL                       =>      TXPRBSSEL_IN,
        ----------------------- Tx Configurable Driver  Ports ----------------------
        TXQPISENN                       =>      open,
        TXQPISENP                       =>      open

--- a/sim/endpoint_mdio.v
+++ b/sim/endpoint_mdio.v
@@ -19,10 +19,20 @@
 `define MDIO_MCR_ANENABLE 32'h00001000
 `define MDIO_MCR_SPEED100_OFFSET 13
 `define MDIO_MCR_SPEED100 32'h00002000
-`define MDIO_MCR_LOOPBACK_OFFSET 14
+`define MDIO_MCR_RESV_OFFSET 14
-`define MDIO_MCR_LOOPBACK 32'h00004000
+`define MDIO_MCR_RESV 32'h00004000
 `define MDIO_MCR_RESET_OFFSET 15
 `define MDIO_MCR_RESET 32'h00008000
+`define MDIO_MCR_LOOPBACK_OFFSET 16
+`define MDIO_MCR_LOOPBACK 32'h00070000
+`define MDIO_MCR_SFP_TX_FAULT_OFFSET 19
+`define MDIO_MCR_SFP_TX_FAULT 32'h00080000
+`define MDIO_MCR_SFP_LOSS_OFFSET 20
+`define MDIO_MCR_SFP_LOSS 32'h00100000
+`define MDIO_MCR_SFP_TX_DISABLE_OFFSET 21
+`define MDIO_MCR_SFP_TX_DISABLE 32'h00200000
+`define MDIO_MCR_TX_PRBS_SEL_OFFSET 22
+`define MDIO_MCR_TX_PRBS_SEL 32'h01c00000
 `define ADDR_MDIO_MSR                  7'h4
 `define MDIO_MSR_ERCAP_OFFSET 0
 `define MDIO_MSR_ERCAP 32'h00000001