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White Rabbit core collection
Commit 241ee64f authored by Guido Visser's avatar Guido Visser Committed by Peter Jansweijer
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hpsec intial commit: dac_refclk signals routed to FMC

parent 54f835c0
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Showing with 67 additions and 15 deletions
top/spec7_write_design/spec7_write_top.vhd
View file @ 241ee64f
......@@ -7,9 +7,10 @@
-------------------------------------------------------------------------------
-- File : spec7_write_top.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Author(s) : Guido Visser HPSEC mods <guidov@nikhef.nl>
-- Company : Nikhef
-- Created : 2018-12-10
-- Last update: 2018-12-10
-- Last update: 2020-06-25
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SPEC7
......@@ -90,10 +91,17 @@ entity spec7_write_top is
-- SPI interface to DACs
---------------------------------------------------------------------------
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
--dac_refclk_cs_n_o : out std_logic;
--dac_refclk_sclk_o : out std_logic;
--dac_refclk_din_o : out std_logic;
dac_refclk_sclk_p_o : out std_logic;
dac_refclk_sclk_n_o : out std_logic;
dac_refclk_din_p_o : out std_logic;
dac_refclk_din_n_o : out std_logic;
dac_refclk_cs_n_p_o : out std_logic;
dac_refclk_cs_n_n_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
......@@ -262,6 +270,10 @@ architecture top of spec7_write_top is
-- Signals
-----------------------------------------------------------------------------
signal dac_refclk_sclk : std_logic;
signal dac_refclk_din : std_logic;
signal dac_refclk_cs_n : std_logic;
-- clock and reset
-- signal clk_125m_pllref : std_logic;
signal clk_sys_62m5 : std_logic;
......@@ -438,9 +450,11 @@ AXI2WB : xwb_axi4lite_bridge
clk_ref_62m5_o => clk_ref_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_62m5_n_o => rst_ref_62m5_n,
dac_refclk_cs_n_o => dac_refclk_cs_n_o,
dac_refclk_sclk_o => dac_refclk_sclk_o,
dac_refclk_din_o => dac_refclk_din_o,
--HPSEC------------------------------------
dac_refclk_sclk_o => dac_refclk_sclk,
dac_refclk_din_o => dac_refclk_din,
dac_refclk_cs_n_o => dac_refclk_cs_n,
dac_dmtd_cs_n_o => dac_dmtd_cs_n_o,
dac_dmtd_sclk_o => dac_dmtd_sclk_o,
dac_dmtd_din_o => dac_dmtd_din_o,
......@@ -524,6 +538,27 @@ AXI2WB : xwb_axi4lite_bridge
O => pps_p_o,
OB => pps_n_o);
------------------------------------------------------------------------------
-- HPSEC this part will pass the DAC SPI to the FMC connnector to the HPSEC
------------------------------------------------------------------------------
dac_refclk_sclk_diff : OBUFDS
port map (
I => dac_refclk_sclk,
O => dac_refclk_sclk_p_o,
OB => dac_refclk_sclk_n_o);
dac_refclk_din_diff : OBUFDS
port map (
I => dac_refclk_din,
O => dac_refclk_din_p_o,
OB => dac_refclk_din_n_o);
dac_refclk_cs_diff : OBUFDS
port map (
I => dac_refclk_cs_n,
O => dac_refclk_cs_n_p_o,
OB => dac_refclk_cs_n_n_o);
-- Type of PPS_IN input:
-- Differential LVDS
-- Or
......
top/spec7_write_design/spec7_write_top.xdc
View file @ 241ee64f
......@@ -6,6 +6,7 @@
# Bank 112 -- 125.000 MHz GTX reference
set_property PACKAGE_PIN U6 [get_ports clk_125m_gtx_p_i]
set_property PACKAGE_PIN U5 [get_ports clk_125m_gtx_n_i]
# Set for extren 125MHz
# Bank 111 -- 125.000 MHz GTX reference
#set_property PACKAGE_PIN W6 [get_ports clk_125m_gtx_p_i]
#set_property PACKAGE_PIN W5 [get_ports clk_125m_gtx_n_i]
......@@ -68,12 +69,16 @@ set_property PACKAGE_PIN E10 [get_ports dac_dmtd_sclk_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_dmtd_sclk_o]
set_property PACKAGE_PIN F12 [get_ports dac_dmtd_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_dmtd_cs_n_o]
set_property PACKAGE_PIN D11 [get_ports dac_refclk_din_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_din_o]
set_property PACKAGE_PIN F10 [get_ports dac_refclk_sclk_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_sclk_o]
set_property PACKAGE_PIN D10 [get_ports dac_refclk_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_cs_n_o]
#set_property PACKAGE_PIN D11 [get_ports dac_refclk_din_o]
#set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_din_o]
#set_property PACKAGE_PIN F10 [get_ports dac_refclk_sclk_o]
#set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_sclk_o]
#set_property PACKAGE_PIN D10 [get_ports dac_refclk_cs_n_o]
#set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_cs_n_o]
# To control the DAC on the HPSEC the dac signals are routed via the FMC connector.
# See below for the pins definitions.
# -------------------------------------------------------------------------------
# -- PLL Control signals
......@@ -371,9 +376,13 @@ set_property IOSTANDARD LVCMOS25 [get_ports pps_i]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 9
#set_property PACKAGE_PIN AE17 [get_ports fmc_la02_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la02_p]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 11
set_property PACKAGE_PIN AE17 [get_ports dac_refclk_sclk_p_o]
set_property IOSTANDARD LVDS_25 [get_ports dac_refclk_sclk_p_o]
#Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 11
#set_property PACKAGE_PIN AF17 [get_ports fmc_la02_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la02_n]
set_property PACKAGE_PIN AF17 [get_ports dac_refclk_sclk_n_o]
set_property IOSTANDARD LVDS_25 [get_ports dac_refclk_sclk_n_o]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 13
#set_property PACKAGE_PIN AA24 [get_ports fmc_la03_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la03_p]
......@@ -383,9 +392,13 @@ set_property IOSTANDARD LVCMOS25 [get_ports pps_i]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 17
#set_property PACKAGE_PIN AE16 [get_ports fmc_la04_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la04_p]
set_property PACKAGE_PIN AE16 [get_ports dac_refclk_din_p_o]
set_property IOSTANDARD LVDS_25 [get_ports dac_refclk_din_p_o]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 19
#set_property PACKAGE_PIN AE15 [get_ports fmc_la04_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la04_n]
set_property PACKAGE_PIN AE15 [get_ports dac_refclk_din_n_o]
set_property IOSTANDARD LVDS_25 [get_ports dac_refclk_din_n_o]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 21
#set_property PACKAGE_PIN W20 [get_ports fmc_la05_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la05_p]
......@@ -401,9 +414,13 @@ set_property IOSTANDARD LVCMOS25 [get_ports pps_i]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 29
#set_property PACKAGE_PIN AB17 [get_ports fmc_la07_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la07_p]
set_property PACKAGE_PIN AB17 [get_ports dac_refclk_cs_n_p_o]
set_property IOSTANDARD LVDS_25 [get_ports dac_refclk_cs_n_p_o]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 31
#set_property PACKAGE_PIN AB16 [get_ports fmc_la07_n]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la07_n]
set_property PACKAGE_PIN AB16 [get_ports dac_refclk_cs_n_n_o]
set_property IOSTANDARD LVDS_25 [get_ports dac_refclk_cs_n_n_o]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 33
#set_property PACKAGE_PIN Y17 [get_ports fmc_la08_p]
#set_property IOSTANDARD LVCMOS25 [get_ports fmc_la08_p]
......
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