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White Rabbit core collection
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20851203
Commit
20851203
authored
Sep 03, 2012
by
Grzegorz Daniluk
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spec_top: follow the changes in wr_gtp_phy_spartan6 module
parent
7592662d
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3 deletions
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-3
spec_top.ucf
top/spec_1_1/wr_core_demo/spec_top.ucf
+0
-3
spec_top.vhd
top/spec_1_1/wr_core_demo/spec_top.vhd
+2
-0
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top/spec_1_1/wr_core_demo/spec_top.ucf
View file @
20851203
...
@@ -628,10 +628,7 @@ NET "fpga_pll_ref_clk_101_n_i" TNM_NET = fpga_pll_ref_clk_101_n_i;
...
@@ -628,10 +628,7 @@ NET "fpga_pll_ref_clk_101_n_i" TNM_NET = fpga_pll_ref_clk_101_n_i;
TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HIGH 50%;
TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HIGH 50%;
PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "U_GTP/U_Rbclk_bufg_ch1.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09
NET "U_GTP/ch0_gtp_clkout_int<1>" TNM_NET = U_GTP/ch0_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch0_gtp_clkout_int_1_ = PERIOD "U_GTP/ch0_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
...
...
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @
20851203
...
@@ -743,6 +743,8 @@ begin
...
@@ -743,6 +743,8 @@ begin
U_GTP
:
wr_gtp_phy_spartan6
U_GTP
:
wr_gtp_phy_spartan6
generic
map
(
generic
map
(
g_enable_ch0
=>
0
,
g_enable_ch1
=>
1
,
g_simulation
=>
0
)
g_simulation
=>
0
)
port
map
(
port
map
(
gtp_clk_i
=>
gtp_dedicated_clk
,
gtp_clk_i
=>
gtp_dedicated_clk
,
...
...
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