Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
2
Merge Requests
2
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
1ef9c93f
Commit
1ef9c93f
authored
Feb 06, 2012
by
Grzegorz Daniluk
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
wrcore_v2: adding endpoint from wishbonized
parent
191b4640
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
21 changed files
with
481 additions
and
367 deletions
+481
-367
Manifest.py
modules/wr_endpoint/Manifest.py
+2
-2
build_wb.sh
modules/wr_endpoint/build_wb.sh
+2
-2
endpoint_pkg.vhd
modules/wr_endpoint/endpoint_pkg.vhd
+4
-2
endpoint_private_pkg.vhd
modules/wr_endpoint/endpoint_private_pkg.vhd
+33
-19
ep_leds_controller.vhd
modules/wr_endpoint/ep_leds_controller.vhd
+105
-0
ep_pcs_tbi_mdio_wb.vhd
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
+1
-1
ep_registers_pkg.vhd
modules/wr_endpoint/ep_registers_pkg.vhd
+1
-1
ep_rtu_header_extract.vhd
modules/wr_endpoint/ep_rtu_header_extract.vhd
+111
-0
ep_rx_buffer.vhd
modules/wr_endpoint/ep_rx_buffer.vhd
+27
-87
ep_rx_early_address_match.vhd
modules/wr_endpoint/ep_rx_early_address_match.vhd
+2
-30
ep_rx_path.vhd
modules/wr_endpoint/ep_rx_path.vhd
+48
-19
ep_rx_pcs_16bit.vhd
modules/wr_endpoint/ep_rx_pcs_16bit.vhd
+2
-2
ep_rx_status_reg_insert.vhd
modules/wr_endpoint/ep_rx_status_reg_insert.vhd
+1
-1
ep_sync_detect_16bit.vhd
modules/wr_endpoint/ep_sync_detect_16bit.vhd
+6
-6
ep_timestamping_unit.vhd
modules/wr_endpoint/ep_timestamping_unit.vhd
+6
-5
ep_tx_framer.vhd
modules/wr_endpoint/ep_tx_framer.vhd
+22
-18
ep_tx_pcs_16bit.vhd
modules/wr_endpoint/ep_tx_pcs_16bit.vhd
+19
-8
ep_wishbone_controller.vhd
modules/wr_endpoint/ep_wishbone_controller.vhd
+1
-1
wr_endpoint.vhd
modules/wr_endpoint/wr_endpoint.vhd
+83
-70
wr_fabric_pkg.vhd
modules/wr_endpoint/wr_fabric_pkg.vhd
+0
-91
xwr_endpoint.vhd
modules/wr_endpoint/xwr_endpoint.vhd
+5
-2
No files found.
modules/wr_endpoint/Manifest.py
View file @
1ef9c93f
...
@@ -19,9 +19,10 @@ files = [ "endpoint_private_pkg.vhd",
...
@@ -19,9 +19,10 @@ files = [ "endpoint_private_pkg.vhd",
"ep_ts_counter.vhd"
,
"ep_ts_counter.vhd"
,
"ep_rx_status_reg_insert.vhd"
,
"ep_rx_status_reg_insert.vhd"
,
"ep_timestamping_unit.vhd"
,
"ep_timestamping_unit.vhd"
,
"ep_leds_controller.vhd"
,
"ep_rtu_header_extract.vhd"
,
# "ep_flow_control.vhd",
# "ep_flow_control.vhd",
# "ep_timestamping_unit.vhd",
# "ep_rmon_counters.vhd",
# "ep_rmon_counters.vhd",
"ep_rx_buffer.vhd"
,
"ep_rx_buffer.vhd"
,
"ep_sync_detect.vhd"
,
"ep_sync_detect.vhd"
,
...
@@ -29,7 +30,6 @@ files = [ "endpoint_private_pkg.vhd",
...
@@ -29,7 +30,6 @@ files = [ "endpoint_private_pkg.vhd",
"ep_wishbone_controller.vhd"
,
"ep_wishbone_controller.vhd"
,
"ep_registers_pkg.vhd"
,
"ep_registers_pkg.vhd"
,
"endpoint_pkg.vhd"
,
"endpoint_pkg.vhd"
,
"wr_fabric_pkg.vhd"
,
"wr_endpoint.vhd"
,
"wr_endpoint.vhd"
,
"xwr_endpoint.vhd"
"xwr_endpoint.vhd"
];
];
modules/wr_endpoint/build_wb.sh
View file @
1ef9c93f
#!/bin/bash
#!/bin/bash
mkdir
-p
doc
mkdir
-p
doc
wbgen2
-D
./doc/wrsw_endpoint.html
-C
endpoint_regs.h
-p
ep_registers_pkg.vhd
-H
record
-V
ep_wishbone_controller.vhd
--cstyle
struct
--lang
vhdl
-K
../../sim/endpoint_regs.v ep_wishbone_controller.wb
~/wbgen2/wishbone-gen/
wbgen2
-D
./doc/wrsw_endpoint.html
-C
endpoint_regs.h
-p
ep_registers_pkg.vhd
-H
record
-V
ep_wishbone_controller.vhd
--cstyle
struct
--lang
vhdl
-K
../../sim/endpoint_regs.v ep_wishbone_controller.wb
wbgen2
-D
./doc/wrsw_endpoint_mdio.html
-V
ep_pcs_tbi_mdio_wb.vhd
--cstyle
defines
--lang
vhdl
-K
../../sim/endpoint_mdio.v pcs_regs.wb
wbgen2
-D
./doc/wrsw_endpoint_mdio.html
-V
ep_pcs_tbi_mdio_wb.vhd
--cstyle
defines
--lang
vhdl
-K
../../sim/endpoint_mdio.v pcs_regs.wb
\ No newline at end of file
modules/wr_endpoint/endpoint_pkg.vhd
View file @
1ef9c93f
...
@@ -12,6 +12,7 @@ package endpoint_pkg is
...
@@ -12,6 +12,7 @@ package endpoint_pkg is
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_simulation
:
boolean
:
=
false
;
g_simulation
:
boolean
:
=
false
;
g_tx_force_gap_length
:
integer
:
=
0
;
g_pcs_16bit
:
boolean
:
=
false
;
g_pcs_16bit
:
boolean
:
=
false
;
g_rx_buffer_size
:
integer
:
=
1024
;
g_rx_buffer_size
:
integer
:
=
1024
;
g_with_rx_buffer
:
boolean
:
=
true
;
g_with_rx_buffer
:
boolean
:
=
true
;
...
@@ -24,7 +25,7 @@ package endpoint_pkg is
...
@@ -24,7 +25,7 @@ package endpoint_pkg is
port
(
port
(
clk_ref_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
:
=
'0'
;
clk_dmtd_i
:
in
std_logic
:
=
'0'
;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
pps_csync_p1_i
:
in
std_logic
:
=
'0'
;
pps_csync_p1_i
:
in
std_logic
:
=
'0'
;
phy_rst_o
:
out
std_logic
;
phy_rst_o
:
out
std_logic
;
...
@@ -101,6 +102,7 @@ package endpoint_pkg is
...
@@ -101,6 +102,7 @@ package endpoint_pkg is
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_simulation
:
boolean
:
=
false
;
g_simulation
:
boolean
:
=
false
;
g_pcs_16bit
:
boolean
:
=
false
;
g_pcs_16bit
:
boolean
:
=
false
;
g_tx_force_gap_length
:
integer
:
=
0
;
g_rx_buffer_size
:
integer
:
=
1024
;
g_rx_buffer_size
:
integer
:
=
1024
;
g_with_rx_buffer
:
boolean
:
=
true
;
g_with_rx_buffer
:
boolean
:
=
true
;
g_with_flow_control
:
boolean
:
=
true
;
g_with_flow_control
:
boolean
:
=
true
;
...
@@ -112,7 +114,7 @@ package endpoint_pkg is
...
@@ -112,7 +114,7 @@ package endpoint_pkg is
port
(
port
(
clk_ref_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
:
=
'0'
;
clk_dmtd_i
:
in
std_logic
:
=
'0'
;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
pps_csync_p1_i
:
in
std_logic
:
=
'0'
;
pps_csync_p1_i
:
in
std_logic
:
=
'0'
;
phy_rst_o
:
out
std_logic
;
phy_rst_o
:
out
std_logic
;
...
...
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @
1ef9c93f
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Created : 2010-11-18
-- Last update: 201
1-10-26
-- Last update: 201
2-01-20
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -46,7 +46,7 @@ use work.ep_wbgen2_pkg.all;
...
@@ -46,7 +46,7 @@ use work.ep_wbgen2_pkg.all;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
package
endpoint_private_pkg
is
package
endpoint_private_pkg
is
-- special/control characters
-- special/control characters
constant
c_k28_5
:
std_logic_vector
(
7
downto
0
)
:
=
"10111100"
;
-- bc
constant
c_k28_5
:
std_logic_vector
(
7
downto
0
)
:
=
"10111100"
;
-- bc
constant
c_k23_7
:
std_logic_vector
(
7
downto
0
)
:
=
"11110111"
;
-- f7
constant
c_k23_7
:
std_logic_vector
(
7
downto
0
)
:
=
"11110111"
;
-- f7
...
@@ -85,23 +85,23 @@ package endpoint_private_pkg is
...
@@ -85,23 +85,23 @@ package endpoint_private_pkg is
prio
:
std_logic_vector
(
2
downto
0
);
prio
:
std_logic_vector
(
2
downto
0
);
has_vid
:
std_logic
;
has_vid
:
std_logic
;
has_prio
:
std_logic
;
has_prio
:
std_logic
;
hash
:
std_logic_vector
(
15
downto
0
);
end
record
;
end
record
;
type
t_rmon_triggers
is
record
type
t_rmon_triggers
is
record
rx_sync_lost
:
std_logic
;
rx_sync_lost
:
std_logic
;
rx_invalid_code
:
std_logic
;
rx_invalid_code
:
std_logic
;
rx_overrun
:
std_logic
;
rx_overrun
:
std_logic
;
rx_crc_err
:
std_logic
;
rx_crc_err
:
std_logic
;
rx_ok
:
std_logic
;
rx_ok
:
std_logic
;
rx_pfilter_drop
:
std_logic
;
rx_pfilter_drop
:
std_logic
;
rx_runt
:
std_logic
;
rx_runt
:
std_logic
;
rx_giant
:
std_logic
;
rx_giant
:
std_logic
;
rx_pause
:
std_logic
;
rx_pause
:
std_logic
;
rx_pcs_err
:
std_logic
;
rx_pcs_err
:
std_logic
;
rx_buffer_overrun
:
std_logic
;
rx_buffer_overrun
:
std_logic
;
rx_rtu_overrun
:
std_logic
;
rx_rtu_overrun
:
std_logic
;
rx_path_timing_failure
:
std_logic
;
rx_path_timing_failure
:
std_logic
;
tx_pause
:
std_logic
;
tx_pause
:
std_logic
;
tx_underrun
:
std_logic
;
tx_underrun
:
std_logic
;
...
@@ -202,7 +202,8 @@ package endpoint_private_pkg is
...
@@ -202,7 +202,8 @@ package endpoint_private_pkg is
component
ep_timestamping_unit
component
ep_timestamping_unit
generic
(
generic
(
g_timestamp_bits_r
:
natural
;
g_timestamp_bits_r
:
natural
;
g_timestamp_bits_f
:
natural
);
g_timestamp_bits_f
:
natural
;
g_ref_clock_rate
:
integer
);
port
(
port
(
clk_ref_i
:
in
std_logic
;
clk_ref_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
...
@@ -285,6 +286,19 @@ package endpoint_private_pkg is
...
@@ -285,6 +286,19 @@ package endpoint_private_pkg is
purge_i
:
in
std_logic
);
purge_i
:
in
std_logic
);
end
component
;
end
component
;
component
ep_leds_controller
generic
(
g_blink_period_log2
:
integer
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
dvalid_tx_i
:
in
std_logic
;
dvalid_rx_i
:
in
std_logic
;
link_ok_i
:
in
std_logic
;
led_link_o
:
out
std_logic
;
led_act_o
:
out
std_logic
);
end
component
;
--function f_pack_fifo_contents (
--function f_pack_fifo_contents (
-- data : std_logic_vector;
-- data : std_logic_vector;
-- sof : std_logic;
-- sof : std_logic;
...
@@ -361,7 +375,7 @@ package body endpoint_private_pkg is
...
@@ -361,7 +375,7 @@ package body endpoint_private_pkg is
else
else
if
(
fab
.
sof
=
'1'
or
fab
.
error
=
'1'
or
fab
.
eof
=
'1'
or
fab
.
has_rx_timestamp
=
'1'
)
then
if
(
fab
.
sof
=
'1'
or
fab
.
error
=
'1'
or
fab
.
eof
=
'1'
or
fab
.
has_rx_timestamp
=
'1'
)
then
-- tag = 01
-- tag = 01
dout
(
17
)
<=
'X'
;
dout
(
17
)
<=
'X'
;
dout
(
16
)
<=
'1'
;
dout
(
16
)
<=
'1'
;
dout
(
15
)
<=
fab
.
sof
;
dout
(
15
)
<=
fab
.
sof
;
dout
(
14
)
<=
fab
.
eof
;
dout
(
14
)
<=
fab
.
eof
;
...
@@ -409,7 +423,7 @@ package body endpoint_private_pkg is
...
@@ -409,7 +423,7 @@ package body endpoint_private_pkg is
fab
.
bytesel
<=
(
not
din
(
16
))
and
din
(
17
);
fab
.
bytesel
<=
(
not
din
(
16
))
and
din
(
17
);
end
if
;
end
if
;
else
else
fab
.
bytesel
<=
'X'
;
fab
.
bytesel
<=
'X'
;
fab
.
dvalid
<=
'0'
;
fab
.
dvalid
<=
'0'
;
fab
.
sof
<=
'0'
;
fab
.
sof
<=
'0'
;
fab
.
eof
<=
'0'
;
fab
.
eof
<=
'0'
;
...
...
modules/wr_endpoint/ep_leds_controller.vhd
0 → 100644
View file @
1ef9c93f
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
endpoint_private_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
entity
ep_leds_controller
is
generic
(
g_blink_period_log2
:
integer
:
=
21
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- data valid (from PCS <> framers)
dvalid_tx_i
:
in
std_logic
;
dvalid_rx_i
:
in
std_logic
;
link_ok_i
:
in
std_logic
;
led_link_o
:
out
std_logic
;
led_act_o
:
out
std_logic
);
end
ep_leds_controller
;
architecture
rtl
of
ep_leds_controller
is
type
t_state
is
(
INACTIVE
,
BLINKING
);
signal
cnt
:
unsigned
(
g_blink_period_log2
-1
downto
0
);
signal
cnt_reset
,
cnt_expired
:
std_logic
;
signal
state
:
t_state
;
signal
led_act
:
std_logic
;
signal
last_cycle_act
:
std_logic
;
signal
txrx
,
txrx_synced
:
std_logic
;
begin
-- rtl
led_link_o
<=
link_ok_i
;
txrx
<=
dvalid_rx_i
or
dvalid_tx_i
;
U_Sync_Activity
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
data_i
=>
txrx
,
synced_o
=>
txrx_synced
);
p_counter
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
or
cnt_reset
=
'1'
)
then
cnt
<=
(
others
=>
'0'
);
else
cnt
<=
cnt
+
1
;
if
((
not
cnt
)
=
0
)
then
cnt_expired
<=
'1'
;
else
cnt_expired
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
p_gen_act_led
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
state
<=
INACTIVE
;
led_act
<=
'0'
;
cnt_reset
<=
'0'
;
else
case
state
is
when
INACTIVE
=>
if
(
txrx_synced
=
'1'
)
then
state
<=
BLINKING
;
led_act
<=
'1'
;
cnt_reset
<=
'1'
;
end
if
;
when
BLINKING
=>
cnt_reset
<=
'0'
;
if
(
cnt_expired
=
'1'
)
then
led_act
<=
not
led_act
;
if
(
last_cycle_act
=
'0'
)
then
led_act
<=
'0'
;
state
<=
INACTIVE
;
end
if
;
last_cycle_act
<=
'0'
;
else
if
(
txrx_synced
=
'1'
)
then
last_cycle_act
<=
'1'
;
end
if
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
led_act_o
<=
led_act
;
end
rtl
;
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
View file @
1ef9c93f
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created :
Sun Nov 6 00:20:16
2011
-- Created :
Wed Oct 26 22:05:09
2011
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
...
...
modules/wr_endpoint/ep_registers_pkg.vhd
View file @
1ef9c93f
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ep_registers_pkg.vhd
-- File : ep_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Sun
Nov 6 00:20:16
2011
-- Created : Sun
Oct 30 00:20:59
2011
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
...
...
modules/wr_endpoint/ep_rtu_header_extract.vhd
0 → 100644
View file @
1ef9c93f
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
endpoint_private_pkg
.
all
;
entity
ep_rtu_header_extract
is
generic
(
g_with_rtu
:
boolean
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_dreq_o
:
out
std_logic
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_dreq_i
:
in
std_logic
;
rtu_rq_o
:
out
t_ep_internal_rtu_request
;
rtu_full_i
:
in
std_logic
;
rtu_rq_valid_o
:
out
std_logic
);
end
ep_rtu_header_extract
;
architecture
rtl
of
ep_rtu_header_extract
is
signal
hdr_offset
:
std_logic_vector
(
11
downto
0
);
signal
in_packet
:
std_logic
;
procedure
f_extract_rtu
(
signal
q
:
out
std_logic_vector
;
signal
fab
:
t_ep_internal_fabric
;
signal
at_offset
:
std_logic
)
is
begin
if
(
at_offset
=
'1'
and
fab
.
dvalid
=
'1'
)
then
q
<=
fab
.
data
;
end
if
;
end
f_extract_rtu
;
begin
-- rtl
gen_with_rtu
:
if
(
g_with_rtu
)
generate
p_hdr_offset_sreg
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
or
snk_fab_i
.
sof
=
'1'
)
then
hdr_offset
(
hdr_offset
'left
downto
1
)
<=
(
others
=>
'0'
);
hdr_offset
(
0
)
<=
'1'
;
elsif
(
snk_fab_i
.
dvalid
=
'1'
)
then
hdr_offset
<=
hdr_offset
(
hdr_offset
'left
-1
downto
0
)
&
'0'
;
end
if
;
end
if
;
end
process
;
p_gen_rtu_request
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
rtu_rq_o
.
smac
<=
(
others
=>
'0'
);
rtu_rq_o
.
dmac
<=
(
others
=>
'0'
);
rtu_rq_o
.
vid
<=
(
others
=>
'0'
);
rtu_rq_o
.
has_vid
<=
'0'
;
rtu_rq_o
.
prio
<=
(
others
=>
'0'
);
rtu_rq_o
.
has_prio
<=
'0'
;
in_packet
<=
'0'
;
else
if
(
snk_fab_i
.
sof
=
'1'
and
rtu_full_i
=
'0'
)
then
in_packet
<=
'1'
;
end
if
;
if
(
snk_fab_i
.
eof
=
'1'
or
snk_fab_i
.
error
=
'1'
)
then
in_packet
<=
'0'
;
end
if
;
f_extract_rtu
(
rtu_rq_o
.
dmac
(
47
downto
32
),
snk_fab_i
,
hdr_offset
(
0
));
f_extract_rtu
(
rtu_rq_o
.
dmac
(
31
downto
16
),
snk_fab_i
,
hdr_offset
(
1
));
f_extract_rtu
(
rtu_rq_o
.
dmac
(
15
downto
0
),
snk_fab_i
,
hdr_offset
(
2
));
f_extract_rtu
(
rtu_rq_o
.
smac
(
47
downto
32
),
snk_fab_i
,
hdr_offset
(
3
));
f_extract_rtu
(
rtu_rq_o
.
smac
(
31
downto
16
),
snk_fab_i
,
hdr_offset
(
4
));
f_extract_rtu
(
rtu_rq_o
.
smac
(
15
downto
0
),
snk_fab_i
,
hdr_offset
(
5
));
if
(
hdr_offset
(
5
)
=
'1'
and
in_packet
=
'1'
)
then
rtu_rq_valid_o
<=
'1'
;
else
rtu_rq_valid_o
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
src_fab_o
.
sof
<=
snk_fab_i
.
sof
and
not
rtu_full_i
;
end
generate
gen_with_rtu
;
gen_without_rtu
:
if
(
not
g_with_rtu
)
generate
src_fab_o
.
sof
<=
snk_fab_i
.
sof
;
end
generate
gen_without_rtu
;
snk_dreq_o
<=
src_dreq_i
;
src_fab_o
.
eof
<=
snk_fab_i
.
eof
;
src_fab_o
.
dvalid
<=
snk_fab_i
.
dvalid
;
src_fab_o
.
error
<=
snk_fab_i
.
error
;
src_fab_o
.
bytesel
<=
snk_fab_i
.
bytesel
;
src_fab_o
.
data
<=
snk_fab_i
.
data
;
src_fab_o
.
addr
<=
snk_fab_i
.
addr
;
src_fab_o
.
has_rx_timestamp
<=
snk_fab_i
.
has_rx_timestamp
;
end
rtl
;
modules/wr_endpoint/ep_rx_buffer.vhd
View file @
1ef9c93f
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Created : 2010-11-18
-- Last update: 201
1-10-29
-- Last update: 201
2-01-23
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -67,15 +67,19 @@ end ep_rx_buffer;
...
@@ -67,15 +67,19 @@ end ep_rx_buffer;
architecture
behavioral
of
ep_rx_buffer
is
architecture
behavioral
of
ep_rx_buffer
is
constant
c_drop_threshold
:
integer
:
=
g_size
*
7
/
8
;
constant
c_drop_threshold
:
integer
:
=
g_size
-
2
;
constant
c_release_threshold
:
integer
:
=
g_size
*
6
/
8
;
constant
c_release_threshold
:
integer
:
=
g_size
*
7
/
8
;
type
t_write_state
is
(
WAIT_FRAME
,
DATA
);
procedure
f_pack_rbuf_contents
procedure
f_pack_rbuf_contents
(
(
signal
st
:
in
t_write_state
;
signal
fab
:
in
t_ep_internal_fabric
;
signal
fab
:
in
t_ep_internal_fabric
;
signal
prev_addr
:
in
std_logic_vector
;
signal
prev_addr
:
in
std_logic_vector
;
signal
dout
:
out
std_logic_vector
;
signal
dout
:
out
std_logic_vector
;
signal
dout_valid
:
out
std_logic
)
is
signal
dout_valid
:
out
std_logic
)
is
variable
valid_tmp
:
std_logic
;
begin
begin
if
(
fab
.
sof
=
'1'
or
fab
.
error
=
'1'
or
fab
.
eof
=
'1'
)
then
if
(
fab
.
sof
=
'1'
or
fab
.
error
=
'1'
or
fab
.
eof
=
'1'
)
then
-- tag = 11
-- tag = 11
...
@@ -85,7 +89,8 @@ architecture behavioral of ep_rx_buffer is
...
@@ -85,7 +89,8 @@ architecture behavioral of ep_rx_buffer is
dout
(
14
)
<=
fab
.
eof
;
dout
(
14
)
<=
fab
.
eof
;
dout
(
13
)
<=
fab
.
error
;
dout
(
13
)
<=
fab
.
error
;
dout
(
12
downto
0
)
<=
(
others
=>
'0'
);
dout
(
12
downto
0
)
<=
(
others
=>
'0'
);
dout_valid
<=
'1'
;
valid_tmp
:
=
'1'
;
-- dout_valid <= '1';
elsif
(
fab
.
dvalid
=
'1'
)
then
elsif
(
fab
.
dvalid
=
'1'
)
then
if
(
prev_addr
/=
fab
.
addr
)
then
if
(
prev_addr
/=
fab
.
addr
)
then
...
@@ -95,12 +100,19 @@ architecture behavioral of ep_rx_buffer is
...
@@ -95,12 +100,19 @@ architecture behavioral of ep_rx_buffer is
end
if
;
end
if
;
dout
(
15
downto
0
)
<=
fab
.
data
;
dout
(
15
downto
0
)
<=
fab
.
data
;
dout_valid
<
=
'1'
;
valid_tmp
:
=
'1'
;
else
else
dout
(
17
downto
0
)
<=
(
others
=>
'0'
);
dout
(
17
downto
0
)
<=
(
others
=>
'0'
);
dout_valid
<
=
'0'
;
valid_tmp
:
=
'0'
;
end
if
;
end
if
;
if
(
fab
.
sof
=
'1'
)
then
dout_valid
<=
valid_tmp
;
elsif
(
st
=
DATA
)
then
dout_valid
<=
valid_tmp
;
else
dout_valid
<=
'0'
;
end
if
;
end
f_pack_rbuf_contents
;
end
f_pack_rbuf_contents
;
procedure
f_unpack_rbuf_contents
procedure
f_unpack_rbuf_contents
...
@@ -155,87 +167,15 @@ architecture behavioral of ep_rx_buffer is
...
@@ -155,87 +167,15 @@ architecture behavioral of ep_rx_buffer is
signal
q_in_valid
,
q_out_valid
:
std_logic
;
signal
q_in_valid
,
q_out_valid
:
std_logic
;
type
t_write_state
is
(
WAIT_FRAME
,
DATA
);
signal
state
:
t_write_state
;
signal
state
:
t_write_state
;
signal
fab_to_encode
:
t_ep_internal_fabric
;
signal
fab_to_encode
:
t_ep_internal_fabric
;
signal
src_fab_int
:
t_ep_internal_fabric
;
signal
src_fab_int
:
t_ep_internal_fabric
;
signal
in_prev_addr
:
std_logic_vector
(
1
downto
0
);
signal
in_prev_addr
:
std_logic_vector
(
1
downto
0
);
signal
out_cur_addr
:
std_logic_vector
(
1
downto
0
);
signal
out_cur_addr
:
std_logic_vector
(
1
downto
0
);
component
chipscope_ila
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
CLK
:
in
std_logic
;
TRIG0
:
in
std_logic_vector
(
31
downto
0
);
TRIG1
:
in
std_logic_vector
(
31
downto
0
);
TRIG2
:
in
std_logic_vector
(
31
downto
0
);
TRIG3
:
in
std_logic_vector
(
31
downto
0
));
end
component
;
component
chipscope_icon
port
(
CONTROL0
:
inout
std_logic_vector
(
35
downto
0
));
end
component
;
signal
CONTROL
:
std_logic_vector
(
35
downto
0
);
signal
CLK
:
std_logic
;
signal
TRIG0
:
std_logic_vector
(
31
downto
0
);
signal
TRIG1
:
std_logic_vector
(
31
downto
0
);
signal
TRIG2
:
std_logic_vector
(
31
downto
0
);
signal
TRIG3
:
std_logic_vector
(
31
downto
0
);
signal
crappify
:
unsigned
(
10
downto
0
);
begin
begin
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_sys_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
TRIG0
(
15
downto
0
)
<=
snk_fab_i
.
data
;
trig0
(
16
)
<=
snk_fab_i
.
sof
;
trig0
(
17
)
<=
snk_fab_i
.
eof
;
trig0
(
18
)
<=
snk_fab_i
.
error
;
trig0
(
19
)
<=
snk_fab_i
.
bytesel
;
trig0
(
20
)
<=
snk_fab_i
.
has_rx_timestamp
;
trig0
(
21
)
<=
snk_fab_i
.
dvalid
;
trig0
(
24
downto
23
)
<=
snk_fab_i
.
addr
;
TRIG1
(
15
downto
0
)
<=
src_fab_int
.
data
;
trig1
(
16
)
<=
src_fab_int
.
sof
;
trig1
(
17
)
<=
src_fab_int
.
eof
;
trig1
(
18
)
<=
src_fab_int
.
error
;
trig1
(
19
)
<=
src_fab_int
.
bytesel
;
trig1
(
20
)
<=
src_fab_int
.
has_rx_timestamp
;
trig1
(
21
)
<=
src_fab_int
.
dvalid
;
trig1
(
24
downto
23
)
<=
src_fab_int
.
addr
;
trig2
(
17
downto
0
)
<=
q_in
;
trig2
(
18
)
<=
q_in_valid
;
trig3
(
17
downto
0
)
<=
q_out
;
trig3
(
18
)
<=
q_empty
;
trig3
(
19
)
<=
q_wr
;
trig3
(
20
)
<=
q_rd
;
trig3
(
21
)
<=
q_drop
;
trig3
(
22
)
<=
q_in_valid
;
trig3
(
23
)
<=
q_out_valid
;
trig3
(
25
downto
24
)
<=
in_prev_addr
;
trig3
(
27
downto
26
)
<=
out_cur_addr
;
p_fifo_write
:
process
(
clk_sys_i
)
p_fifo_write
:
process
(
clk_sys_i
)
begin
begin
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
...
@@ -277,10 +217,10 @@ begin
...
@@ -277,10 +217,10 @@ begin
end
if
;
end
if
;
end
process
;
end
process
;
p_pack_rbuf
:
process
(
fab_to_encode
,
in_prev_addr
)
p_pack_rbuf
:
process
(
state
,
fab_to_encode
,
in_prev_addr
)
begin
begin
f_pack_rbuf_contents
(
fab_to_encode
,
in_prev_addr
,
q_in
,
q_in_valid
);
f_pack_rbuf_contents
(
state
,
fab_to_encode
,
in_prev_addr
,
q_in
,
q_in_valid
);
end
process
;
end
process
;
p_encode_fifo_in
:
process
(
snk_fab_i
,
state
,
q_drop
)
p_encode_fifo_in
:
process
(
snk_fab_i
,
state
,
q_drop
)
...
@@ -321,15 +261,15 @@ begin
...
@@ -321,15 +261,15 @@ begin
almost_full_o
=>
open
,
almost_full_o
=>
open
,
count_o
=>
q_usedw
);
count_o
=>
q_usedw
);
q_rd
<=
(
not
q_empty
)
and
src_dreq_i
;
q_rd
<=
(
not
q_empty
)
and
src_dreq_i
;
rd_valid_gen
:
process
(
clk_sys_i
)
rd_valid_gen
:
process
(
clk_sys_i
)
begin
begin
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
q_out_valid
<=
'0'
;
q_out_valid
<=
'0'
;
out_cur_addr
<=
c_WRF_STATUS
;
out_cur_addr
<=
c_WRF_STATUS
;
else
else
q_out_valid
<=
q_rd
;
q_out_valid
<=
q_rd
;
...
@@ -343,7 +283,7 @@ begin
...
@@ -343,7 +283,7 @@ begin
end
if
;
end
if
;
end
process
;
end
process
;
p_unpack
:
process
(
q_out
,
out_cur_addr
,
q_out_valid
)
p_unpack
:
process
(
q_out
,
out_cur_addr
,
q_out_valid
)
begin
begin
f_unpack_rbuf_contents
(
q_out
,
out_cur_addr
,
q_out_valid
,
src_fab_int
);
f_unpack_rbuf_contents
(
q_out
,
out_cur_addr
,
q_out_valid
,
src_fab_int
);
end
process
;
end
process
;
...
...
modules/wr_endpoint/ep_rx_early_address_match.vhd
View file @
1ef9c93f
...
@@ -11,8 +11,6 @@ use work.ep_wbgen2_pkg.all;
...
@@ -11,8 +11,6 @@ use work.ep_wbgen2_pkg.all;
-- to filter out pause and HP frames in advance.
-- to filter out pause and HP frames in advance.
entity
ep_rx_early_address_match
is
entity
ep_rx_early_address_match
is
generic
(
g_with_rtu
:
boolean
);
port
(
port
(
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_rx_i
:
in
std_logic
;
clk_rx_i
:
in
std_logic
;
...
@@ -28,8 +26,6 @@ entity ep_rx_early_address_match is
...
@@ -28,8 +26,6 @@ entity ep_rx_early_address_match is
match_is_pause_o
:
out
std_logic
;
match_is_pause_o
:
out
std_logic
;
match_pause_quanta_o
:
out
std_logic_vector
(
15
downto
0
);
match_pause_quanta_o
:
out
std_logic_vector
(
15
downto
0
);
rtu_rq_o
:
out
t_ep_internal_rtu_request
;
regs_i
:
in
t_ep_out_registers
regs_i
:
in
t_ep_out_registers
);
);
...
@@ -56,14 +52,7 @@ architecture behavioral of ep_rx_early_address_match is
...
@@ -56,14 +52,7 @@ architecture behavioral of ep_rx_early_address_match is
end
if
;
end
if
;
end
f_compare_slv
;
end
f_compare_slv
;
procedure
f_extract_rtu
(
signal
q
:
out
std_logic_vector
;
signal
fab
:
t_ep_internal_fabric
;
signal
at_offset
:
std_logic
)
is
begin
if
(
at_offset
=
'1'
and
fab
.
dvalid
=
'1'
)
then
q
<=
fab
.
data
;
end
if
;
end
f_extract_rtu
;
begin
-- behavioral
begin
-- behavioral
...
@@ -126,24 +115,7 @@ begin -- behavioral
...
@@ -126,24 +115,7 @@ begin -- behavioral
end
if
;
end
if
;
end
process
;
end
process
;
gen_with_rtu
:
if
(
g_with_rtu
)
generate
p_gen_rtu_request
:
process
(
clk_rx_i
)
begin
if
rising_edge
(
clk_rx_i
)
then
if
rst_n_rx_i
=
'0'
then
rtu_rq_o
.
smac
<=
(
others
=>
'0'
);
rtu_rq_o
.
dmac
<=
(
others
=>
'0'
);
else
f_extract_rtu
(
rtu_rq_o
.
dmac
(
47
downto
32
),
snk_fab_i
,
hdr_offset
(
0
));
f_extract_rtu
(
rtu_rq_o
.
dmac
(
31
downto
16
),
snk_fab_i
,
hdr_offset
(
1
));
f_extract_rtu
(
rtu_rq_o
.
dmac
(
15
downto
0
),
snk_fab_i
,
hdr_offset
(
2
));
f_extract_rtu
(
rtu_rq_o
.
smac
(
47
downto
32
),
snk_fab_i
,
hdr_offset
(
3
));
f_extract_rtu
(
rtu_rq_o
.
smac
(
31
downto
16
),
snk_fab_i
,
hdr_offset
(
4
));
f_extract_rtu
(
rtu_rq_o
.
smac
(
15
downto
0
),
snk_fab_i
,
hdr_offset
(
5
));
end
if
;
end
if
;
end
process
;
end
generate
gen_with_rtu
;
p_match_hp
:
process
(
clk_rx_i
)
p_match_hp
:
process
(
clk_rx_i
)
...
...
modules/wr_endpoint/ep_rx_path.vhd
View file @
1ef9c93f
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Created : 2009-06-22
-- Last update: 201
1-10-29
-- Last update: 201
2-01-23
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -101,9 +101,22 @@ end ep_rx_path;
...
@@ -101,9 +101,22 @@ end ep_rx_path;
architecture
behavioral
of
ep_rx_path
is
architecture
behavioral
of
ep_rx_path
is
component
ep_r
x_early_address_match
component
ep_r
tu_header_extract
generic
(
generic
(
g_with_rtu
:
boolean
);
g_with_rtu
:
boolean
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
snk_fab_i
:
in
t_ep_internal_fabric
;
snk_dreq_o
:
out
std_logic
;
src_fab_o
:
out
t_ep_internal_fabric
;
src_dreq_i
:
in
std_logic
;
rtu_rq_o
:
out
t_ep_internal_rtu_request
;
rtu_full_i
:
in
std_logic
;
rtu_rq_valid_o
:
out
std_logic
);
end
component
;
component
ep_rx_early_address_match
port
(
port
(
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_rx_i
:
in
std_logic
;
clk_rx_i
:
in
std_logic
;
...
@@ -115,7 +128,6 @@ architecture behavioral of ep_rx_path is
...
@@ -115,7 +128,6 @@ architecture behavioral of ep_rx_path is
match_is_hp_o
:
out
std_logic
;
match_is_hp_o
:
out
std_logic
;
match_is_pause_o
:
out
std_logic
;
match_is_pause_o
:
out
std_logic
;
match_pause_quanta_o
:
out
std_logic_vector
(
15
downto
0
);
match_pause_quanta_o
:
out
std_logic_vector
(
15
downto
0
);
rtu_rq_o
:
out
t_ep_internal_rtu_request
;
regs_i
:
in
t_ep_out_registers
);
regs_i
:
in
t_ep_out_registers
);
end
component
;
end
component
;
...
@@ -189,6 +201,8 @@ architecture behavioral of ep_rx_path is
...
@@ -189,6 +201,8 @@ architecture behavioral of ep_rx_path is
end
component
;
end
component
;
component
ep_rx_wb_master
component
ep_rx_wb_master
generic
(
g_ignore_ack
:
boolean
);
port
(
port
(
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
@@ -261,8 +275,8 @@ architecture behavioral of ep_rx_path is
...
@@ -261,8 +275,8 @@ architecture behavioral of ep_rx_path is
type
t_fab_pipe
is
array
(
integer
range
<>
)
of
t_ep_internal_fabric
;
type
t_fab_pipe
is
array
(
integer
range
<>
)
of
t_ep_internal_fabric
;
signal
fab_pipe
:
t_fab_pipe
(
0
to
8
);
signal
fab_pipe
:
t_fab_pipe
(
0
to
9
);
signal
dreq_pipe
:
std_logic_vector
(
8
downto
0
);
signal
dreq_pipe
:
std_logic_vector
(
9
downto
0
);
signal
ematch_done
:
std_logic
;
signal
ematch_done
:
std_logic
;
signal
ematch_is_hp
:
std_logic
;
signal
ematch_is_hp
:
std_logic
;
...
@@ -285,8 +299,6 @@ begin -- behavioral
...
@@ -285,8 +299,6 @@ begin -- behavioral
fab_pipe
(
0
)
<=
pcs_fab_i
;
fab_pipe
(
0
)
<=
pcs_fab_i
;
U_early_addr_match
:
ep_rx_early_address_match
U_early_addr_match
:
ep_rx_early_address_match
generic
map
(
g_with_rtu
=>
g_with_rtu
)
port
map
(
port
map
(
clk_sys_i
=>
clk_sys_i
,
clk_sys_i
=>
clk_sys_i
,
...
@@ -380,19 +392,34 @@ begin -- behavioral
...
@@ -380,19 +392,34 @@ begin -- behavioral
regs_i
=>
regs_i
);
regs_i
=>
regs_i
);
end
generate
gen_with_vlan_unit
;
end
generate
gen_with_vlan_unit
;
gen_without_vlan_unit
:
if
(
not
g_with_vlans
)
generate
gen_without_vlan_unit
:
if
(
not
g_with_vlans
)
generate
fab_pipe
(
6
)
<=
fab_pipe
(
5
);
fab_pipe
(
6
)
<=
fab_pipe
(
5
);
dreq_pipe
(
5
)
<=
dreq_pipe
(
6
);
dreq_pipe
(
5
)
<=
dreq_pipe
(
6
);
end
generate
gen_without_vlan_unit
;
end
generate
gen_without_vlan_unit
;
U_RTU_Header_Extract
:
ep_rtu_header_extract
generic
map
(
g_with_rtu
=>
g_with_rtu
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
snk_fab_i
=>
fab_pipe
(
6
),
snk_dreq_o
=>
dreq_pipe
(
6
),
src_fab_o
=>
fab_pipe
(
7
),
src_dreq_i
=>
dreq_pipe
(
7
),
rtu_rq_o
=>
rtu_rq_o
,
rtu_full_i
=>
rtu_full_i
,
rtu_rq_valid_o
=>
rtu_rq_valid_o
);
U_Gen_Status
:
ep_rx_status_reg_insert
U_Gen_Status
:
ep_rx_status_reg_insert
port
map
(
port
map
(
clk_sys_i
=>
clk_sys_i
,
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
snk_fab_i
=>
fab_pipe
(
6
),
snk_fab_i
=>
fab_pipe
(
7
),
snk_dreq_o
=>
dreq_pipe
(
6
),
snk_dreq_o
=>
dreq_pipe
(
7
),
src_fab_o
=>
fab_pipe
(
7
),
src_fab_o
=>
fab_pipe
(
8
),
src_dreq_i
=>
dreq_pipe
(
7
),
src_dreq_i
=>
dreq_pipe
(
8
),
pfilter_drop_i
=>
pfilter_drop
,
pfilter_drop_i
=>
pfilter_drop
,
pfilter_pclass_i
=>
pfilter_pclass
,
pfilter_pclass_i
=>
pfilter_pclass
,
pfilter_done_i
=>
pfilter_done
,
pfilter_done_i
=>
pfilter_done
,
...
@@ -408,26 +435,28 @@ begin -- behavioral
...
@@ -408,26 +435,28 @@ begin -- behavioral
port
map
(
port
map
(
clk_sys_i
=>
clk_sys_i
,
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
snk_fab_i
=>
fab_pipe
(
7
),
snk_fab_i
=>
fab_pipe
(
8
),
snk_dreq_o
=>
dreq_pipe
(
7
),
snk_dreq_o
=>
dreq_pipe
(
8
),
src_fab_o
=>
fab_pipe
(
8
),
src_fab_o
=>
fab_pipe
(
9
),
src_dreq_i
=>
dreq_pipe
(
8
),
src_dreq_i
=>
dreq_pipe
(
9
),
level_o
=>
fc_buffer_occupation_o
,
level_o
=>
fc_buffer_occupation_o
,
regs_i
=>
regs_i
,
regs_i
=>
regs_i
,
rmon_o
=>
open
);
rmon_o
=>
open
);
end
generate
gen_with_rx_buffer
;
end
generate
gen_with_rx_buffer
;
gen_without_rx_buffer
:
if
(
not
g_with_rx_buffer
)
generate
gen_without_rx_buffer
:
if
(
not
g_with_rx_buffer
)
generate
fab_pipe
(
8
)
<=
fab_pipe
(
7
);
fab_pipe
(
9
)
<=
fab_pipe
(
8
);
dreq_pipe
(
7
)
<=
dreq_pipe
(
8
);
dreq_pipe
(
8
)
<=
dreq_pipe
(
9
);
end
generate
gen_without_rx_buffer
;
end
generate
gen_without_rx_buffer
;
U_RX_Wishbone_Master
:
ep_rx_wb_master
U_RX_Wishbone_Master
:
ep_rx_wb_master
generic
map
(
g_ignore_ack
=>
true
)
port
map
(
port
map
(
clk_sys_i
=>
clk_sys_i
,
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
rst_n_i
=>
rst_n_sys_i
,
snk_fab_i
=>
fab_pipe
(
8
),
snk_fab_i
=>
fab_pipe
(
9
),
snk_dreq_o
=>
dreq_pipe
(
8
),
snk_dreq_o
=>
dreq_pipe
(
9
),
src_wb_i
=>
src_wb_i
,
src_wb_i
=>
src_wb_i
,
src_wb_o
=>
src_wb_o
src_wb_o
=>
src_wb_o
);
);
...
...
modules/wr_endpoint/ep_rx_pcs_16bit.vhd
View file @
1ef9c93f
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Created : 2009-06-16
-- Last update: 201
1-10-07
-- Last update: 201
2-01-18
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -387,7 +387,7 @@ begin
...
@@ -387,7 +387,7 @@ begin
phy_rx_data_i
(
15
downto
8
)
=
c_K28_5
phy_rx_data_i
(
15
downto
8
)
=
c_K28_5
and
(
phy_rx_data_i
(
7
downto
0
)
=
c_d21_5
and
(
phy_rx_data_i
(
7
downto
0
)
=
c_d21_5
or
phy_rx_data_i
(
7
downto
0
)
=
c_d2_2
)
or
phy_rx_data_i
(
7
downto
0
)
=
c_d2_2
)
and
phy_rx_k_i
=
"1
1
"
);
and
phy_rx_k_i
=
"1
0
"
);
-- invalid code received?
-- invalid code received?
...
...
modules/wr_endpoint/ep_rx_status_reg_insert.vhd
View file @
1ef9c93f
...
@@ -132,7 +132,7 @@ begin -- rtl
...
@@ -132,7 +132,7 @@ begin -- rtl
sreg
.
match_class
<=
pfilter_pclass_i
;
sreg
.
match_class
<=
pfilter_pclass_i
;
sreg
.
is_hp
<=
ematch_is_hp_i
;
sreg
.
is_hp
<=
ematch_is_hp_i
;
sreg
.
has_crc
<=
'
1
'
;
sreg
.
has_crc
<=
'
0
'
;
sreg
.
has_smac
<=
'1'
;
sreg
.
has_smac
<=
'1'
;
sreg
.
error
<=
'0'
;
sreg
.
error
<=
'0'
;
end
if
;
end
if
;
...
...
modules/wr_endpoint/ep_sync_detect_16bit.vhd
View file @
1ef9c93f
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Company : CERN BE-Co-HT
-- Created : 2010-05-28
-- Created : 2010-05-28
-- Last update: 201
1-10-14
-- Last update: 201
2-01-18
-- Platform : FPGA-generics
-- Platform : FPGA-generics
-- Standard : VHDL
-- Standard : VHDL
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -76,11 +76,12 @@ architecture behavioral of ep_sync_detect_16bit is
...
@@ -76,11 +76,12 @@ architecture behavioral of ep_sync_detect_16bit is
signal
valid_idle
:
std_logic
;
signal
valid_idle
:
std_logic
;
signal
invalid_code
:
std_logic
;
signal
invalid_code
:
std_logic
;
signal
valid_data
:
std_logic
;
begin
-- behavioral
begin
-- behavioral
valid_idle
<=
'1'
when
(
k_i
=
"10"
and
data_i
(
15
downto
8
)
=
c_k28_5
and
err_i
=
'0'
)
else
'0'
;
valid_idle
<=
'1'
when
(
k_i
=
"10"
and
data_i
(
15
downto
8
)
=
c_k28_5
and
err_i
=
'0'
)
else
'0'
;
valid_data
<=
'1'
when
(
k_i
=
"00"
and
err_i
=
'0'
)
else
'0'
;
invalid_code
<=
'1'
when
(
err_i
=
'1'
or
(
k_i
(
0
)
=
'1'
and
data_i
(
7
downto
0
)
=
c_k28_5
))
else
'0'
;
invalid_code
<=
'1'
when
(
err_i
=
'1'
or
(
k_i
(
0
)
=
'1'
and
data_i
(
7
downto
0
)
=
c_k28_5
))
else
'0'
;
...
@@ -105,13 +106,12 @@ begin -- behavioral
...
@@ -105,13 +106,12 @@ begin -- behavioral
when
LOSS_OF_SYNC
=>
when
LOSS_OF_SYNC
=>
synced_o
<=
'0'
;
synced_o
<=
'0'
;
state
<=
f_pick
(
valid_idle
,
CD_ACQ_1
,
LOSS_OF_SYNC
);
state
<=
f_pick
(
valid_idle
,
CD_ACQ_1
,
LOSS_OF_SYNC
);
when
CD_ACQ_1
=>
when
CD_ACQ_1
=>
state
<=
f_pick
(
valid_idle
,
CD_ACQ_2
,
LOSS_OF_SYNC
);
state
<=
f_pick
(
valid_idle
or
valid_data
,
CD_ACQ_2
,
LOSS_OF_SYNC
);
when
CD_ACQ_2
=>
when
CD_ACQ_2
=>
state
<=
f_pick
(
valid_idle
,
CD_ACQ_3
,
LOSS_OF_SYNC
);
state
<=
f_pick
(
valid_idle
,
CD_ACQ_3
,
LOSS_OF_SYNC
);
when
CD_ACQ_3
=>
when
CD_ACQ_3
=>
state
<=
f_pick
(
valid_idle
,
SYNC_ACQUIRED_1
,
LOSS_OF_SYNC
);
state
<=
f_pick
(
valid_idle
or
valid_data
,
SYNC_ACQUIRED_1
,
LOSS_OF_SYNC
);
when
SYNC_ACQUIRED_1
=>
when
SYNC_ACQUIRED_1
=>
synced_o
<=
'1'
;
synced_o
<=
'1'
;
...
...
modules/wr_endpoint/ep_timestamping_unit.vhd
View file @
1ef9c93f
...
@@ -7,7 +7,7 @@
...
@@ -7,7 +7,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Created : 2009-06-22
-- Last update: 201
1-10-06
-- Last update: 201
2-01-20
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'87
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -43,7 +43,8 @@ entity ep_timestamping_unit is
...
@@ -43,7 +43,8 @@ entity ep_timestamping_unit is
-- size of rising edge timestamp
-- size of rising edge timestamp
g_timestamp_bits_r
:
natural
:
=
28
;
g_timestamp_bits_r
:
natural
:
=
28
;
-- size of falling edge timestamp
-- size of falling edge timestamp
g_timestamp_bits_f
:
natural
:
=
4
g_timestamp_bits_f
:
natural
:
=
4
;
g_ref_clock_rate
:
integer
:
=
125000000
);
);
port
(
port
(
...
@@ -174,7 +175,7 @@ begin -- syn
...
@@ -174,7 +175,7 @@ begin -- syn
g_num_bits_r
=>
g_timestamp_bits_r
,
g_num_bits_r
=>
g_timestamp_bits_r
,
g_num_bits_f
=>
g_timestamp_bits_f
,
g_num_bits_f
=>
g_timestamp_bits_f
,
g_init_value
=>
0
,
g_init_value
=>
0
,
g_max_value
=>
124999999
)
g_max_value
=>
g_ref_clock_rate
-1
)
port
map
(
port
map
(
clk_i
=>
clk_ref_i
,
clk_i
=>
clk_ref_i
,
...
@@ -306,6 +307,7 @@ begin -- syn
...
@@ -306,6 +307,7 @@ begin -- syn
-- TX OOB & timestamp combiner
-- TX OOB & timestamp combiner
tx_oob_stuff
:
process
(
clk_sys_i
)
tx_oob_stuff
:
process
(
clk_sys_i
)
begin
-- process
begin
-- process
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
...
@@ -359,7 +361,6 @@ begin -- syn
...
@@ -359,7 +361,6 @@ begin -- syn
end
if
;
end
if
;
end
process
;
end
process
;
txtsu_port_id_o
<=
regs_i
.
ecr_portid_o
;
end
syn
;
end
syn
;
modules/wr_endpoint/ep_tx_framer.vhd
View file @
1ef9c93f
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Created : 2009-06-22
-- Last update: 201
1-09-11
-- Last update: 201
2-01-23
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'87
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -40,7 +40,8 @@ use work.ep_wbgen2_pkg.all;
...
@@ -40,7 +40,8 @@ use work.ep_wbgen2_pkg.all;
entity
ep_tx_framer
is
entity
ep_tx_framer
is
generic
(
generic
(
g_with_vlans
:
boolean
;
g_with_vlans
:
boolean
;
g_with_timestamper
:
boolean
g_with_timestamper
:
boolean
;
g_force_gap_length
:
integer
);
);
port
(
port
(
...
@@ -92,7 +93,7 @@ entity ep_tx_framer is
...
@@ -92,7 +93,7 @@ entity ep_tx_framer is
-- control registers
-- control registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
regs_i
:
in
t_ep_out_registers
regs_i
:
in
t_ep_out_registers
);
);
...
@@ -267,29 +268,27 @@ begin -- behavioral
...
@@ -267,29 +268,27 @@ begin -- behavioral
p_oob_fsm
:
process
(
clk_sys_i
)
p_oob_fsm
:
process
(
clk_sys_i
)
begin
begin
if
rising_edge
(
clk_sys_i
)
then
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
or
sof_p1
=
'1'
)
then
oob_state
<=
OOB_
IDLE
;
oob_state
<=
OOB_
1
;
oob
.
valid
<=
'0'
;
oob
.
valid
<=
'0'
;
oob
.
oob_type
<=
(
others
=>
'0'
);
oob
.
oob_type
<=
(
others
=>
'0'
);
else
else
case
oob_state
is
case
oob_state
is
when
OOB_IDLE
=>
if
sof_p1
=
'1'
then
oob_state
<=
OOB_1
;
OOB
.
valid
<=
'0'
;
end
if
;
when
OOB_1
=>
when
OOB_1
=>
if
(
snk_valid
=
'1'
and
snk_i
.
adr
=
c_WRF_OOB
)
then
if
(
snk_valid
=
'1'
and
snk_i
.
adr
=
c_WRF_OOB
)
then
oob
.
oob_type
<=
snk_i
.
dat
(
15
downto
12
);
oob
.
oob_type
<=
snk_i
.
dat
(
15
downto
12
);
oob_state
<=
OOB_2
;
oob_state
<=
OOB_2
;
end
if
;
end
if
;
when
OOB_2
=>
when
OOB_2
=>
if
(
snk_valid
=
'1'
and
snk_i
.
adr
=
c_WRF_OOB
)
then
if
(
snk_valid
=
'1'
and
snk_i
.
adr
=
c_WRF_OOB
and
oob
.
oob_type
=
c_WRF_OOB_TYPE_TX
)
then
oob
.
frame_id
<=
snk_i
.
dat
(
15
downto
0
);
oob
.
frame_id
<=
snk_i
.
dat
(
15
downto
0
);
oob_state
<=
OOB_IDLE
;
oob_state
<=
OOB_IDLE
;
oob
.
valid
<=
'1'
;
oob
.
valid
<=
'1'
;
end
if
;
end
if
;
when
OOB_IDLE
=>
oob_state
<=
OOB_IDLE
;
end
case
;
end
case
;
end
if
;
end
if
;
end
if
;
end
if
;
...
@@ -612,8 +611,7 @@ begin -- behavioral
...
@@ -612,8 +611,7 @@ begin -- behavioral
else
-- CRC at even position
else
-- CRC at even position
q_eof
<=
'1'
;
q_eof
<=
'1'
;
q_data
(
15
downto
0
)
<=
crc_value
(
15
downto
0
);
q_data
(
15
downto
0
)
<=
crc_value
(
15
downto
0
);
counter
<=
to_unsigned
(
g_force_gap_length
,
counter
'length
);
counter
<=
(
others
=>
'0'
);
tx_ready
<=
'0'
;
tx_ready
<=
'0'
;
state
<=
TXF_GAP
;
state
<=
TXF_GAP
;
end
if
;
end
if
;
...
@@ -626,7 +624,7 @@ begin -- behavioral
...
@@ -626,7 +624,7 @@ begin -- behavioral
counter
<=
(
others
=>
'0'
);
counter
<=
(
others
=>
'0'
);
tx_ready
<=
'0'
;
tx_ready
<=
'0'
;
state
<=
TXF_GAP
;
state
<=
TXF_GAP
;
counter
<=
to_unsigned
(
g_force_gap_length
,
counter
'length
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TX FSM states: WAIT_CRC, EMBED_CRC: dealing with frame checksum field
-- TX FSM states: WAIT_CRC, EMBED_CRC: dealing with frame checksum field
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -639,12 +637,18 @@ begin -- behavioral
...
@@ -639,12 +637,18 @@ begin -- behavioral
snk_out
.
rty
<=
'0'
;
snk_out
.
rty
<=
'0'
;
q_bytesel
<=
'0'
;
q_bytesel
<=
'0'
;
if
(
oob
.
valid
=
'1'
)
then
if
(
counter
=
0
or
g_force_gap_length
=
0
)
then
if
(
pcs_busy_i
=
'0'
)
then
if
(
oob
.
valid
=
'1'
)
then
if
(
pcs_busy_i
=
'0'
)
then
state
<=
TXF_IDLE
;
end
if
;
else
state
<=
TXF_IDLE
;
state
<=
TXF_IDLE
;
end
if
;
end
if
;
else
else
state
<=
TXF_IDLE
;
counter
<=
counter
-
1
;
end
if
;
end
if
;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -671,7 +675,7 @@ begin -- behavioral
...
@@ -671,7 +675,7 @@ begin -- behavioral
stall_int
<=
not
(
pcs_dreq_i
and
tx_ready
)
and
regs_i
.
ecr_tx_en_o
;
-- /dev/null if disabled
stall_int
<=
not
(
pcs_dreq_i
and
tx_ready
)
and
regs_i
.
ecr_tx_en_o
;
-- /dev/null if disabled
snk_out
.
stall
<=
stall_int
;
snk_out
.
stall
<=
stall_int
or
(
not
snk_i
.
cyc
and
snk_cyc_d0
)
;
p_gen_ack
:
process
(
clk_sys_i
)
p_gen_ack
:
process
(
clk_sys_i
)
begin
begin
...
...
modules/wr_endpoint/ep_tx_pcs_16bit.vhd
View file @
1ef9c93f
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT section
-- Company : CERN BE-CO-HT section
-- Created : 2009-06-16
-- Created : 2009-06-16
-- Last update: 201
1-10-05
-- Last update: 201
2-01-23
-- Platform : FPGA-generic
-- Platform : FPGA-generic
-- Standard : VHDL'93
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -145,10 +145,20 @@ architecture behavioral of ep_tx_pcs_16bit is
...
@@ -145,10 +145,20 @@ architecture behavioral of ep_tx_pcs_16bit is
signal
reset_synced_txclk
:
std_logic
;
signal
reset_synced_txclk
:
std_logic
;
signal
mdio_mcr_pdown_synced
:
std_logic
;
signal
mdio_mcr_pdown_synced
:
std_logic
;
signal
s_one
:
std_logic
:
=
'1'
;
signal
s_one
:
std_logic
:
=
'1'
;
signal
an_tx_en_synced
:
std_logic
;
begin
begin
U_sync_an_tx_en
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
port
map
(
clk_i
=>
phy_tx_clk_i
,
rst_n_i
=>
rst_n_i
,
data_i
=>
an_tx_en_i
,
synced_o
=>
an_tx_en_synced
);
U_sync_pcs_busy_o
:
gc_sync_ffs
U_sync_pcs_busy_o
:
gc_sync_ffs
generic
map
(
generic
map
(
g_sync_edge
=>
"positive"
)
g_sync_edge
=>
"positive"
)
...
@@ -206,7 +216,7 @@ begin
...
@@ -206,7 +216,7 @@ begin
g_with_rd_almost_empty
=>
true
,
g_with_rd_almost_empty
=>
true
,
g_with_rd_count
=>
true
,
g_with_rd_count
=>
true
,
g_with_wr_almost_full
=>
true
,
g_with_wr_almost_full
=>
true
,
g_almost_empty_threshold
=>
16
,
g_almost_empty_threshold
=>
32
,
g_almost_full_threshold
=>
56
)
-- fixme: make this a generic (or WB register)
g_almost_full_threshold
=>
56
)
-- fixme: make this a generic (or WB register)
port
map
(
port
map
(
rst_n_i
=>
fifo_clear_n
,
rst_n_i
=>
fifo_clear_n
,
...
@@ -281,7 +291,7 @@ begin
...
@@ -281,7 +291,7 @@ begin
-- endpoint wants to send Config_Reg
-- endpoint wants to send Config_Reg
if
(
an_tx_en_
i
=
'1'
)
then
if
(
an_tx_en_
synced
=
'1'
)
then
tx_state
<=
TX_CR12
;
tx_state
<=
TX_CR12
;
tx_cr_alternate
<=
'0'
;
tx_cr_alternate
<=
'0'
;
fifo_rd
<=
'0'
;
fifo_rd
<=
'0'
;
...
@@ -320,7 +330,7 @@ begin
...
@@ -320,7 +330,7 @@ begin
when
TX_CAL
=>
when
TX_CAL
=>
tx_is_k
<=
"11"
;
tx_is_k
<=
"11"
;
tx_odata_reg
<=
c_k28_7
&
c_k28_7
;
tx_odata_reg
<=
c_k28_7
&
c_k28_7
;
tx_cr_alternate
<=
'1'
;
if
(
mdio_wr_spec_tx_cal_i
=
'0'
and
tx_cr_alternate
=
'1'
)
then
if
(
mdio_wr_spec_tx_cal_i
=
'0'
and
tx_cr_alternate
=
'1'
)
then
tx_state
<=
TX_COMMA_IDLE
;
tx_state
<=
TX_COMMA_IDLE
;
end
if
;
end
if
;
...
@@ -343,10 +353,11 @@ begin
...
@@ -343,10 +353,11 @@ begin
tx_state
<=
TX_CR34
;
tx_state
<=
TX_CR34
;
when
TX_CR34
=>
when
TX_CR34
=>
tx_is_k
<=
"00"
;
tx_odata_reg
(
15
downto
8
)
<=
an_tx_val_i
(
7
downto
0
);
tx_odata_reg
(
15
downto
8
)
<=
an_tx_val_i
(
7
downto
0
);
tx_odata_reg
(
7
downto
0
)
<=
an_tx_val_i
(
15
downto
8
);
tx_odata_reg
(
7
downto
0
)
<=
an_tx_val_i
(
15
downto
8
);
if
(
an_tx_en_
i
=
'1'
)
then
if
(
an_tx_en_
synced
=
'1'
)
then
tx_state
<=
TX_CR12
;
tx_state
<=
TX_CR12
;
else
else
tx_state
<=
TX_COMMA_IDLE
;
tx_state
<=
TX_COMMA_IDLE
;
...
@@ -432,7 +443,7 @@ begin
...
@@ -432,7 +443,7 @@ begin
tx_is_k
<=
"11"
;
tx_is_k
<=
"11"
;
tx_odata_reg
<=
c_k23_7
&
c_k23_7
;
tx_odata_reg
<=
c_k23_7
&
c_k23_7
;
tx_catch_disparity
<=
'1'
;
tx_catch_disparity
<=
'1'
;
tx_cntr
<=
"
10
00"
;
tx_cntr
<=
"
01
00"
;
tx_state
<=
TX_COMMA_IDLE
;
tx_state
<=
TX_COMMA_IDLE
;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -446,7 +457,7 @@ begin
...
@@ -446,7 +457,7 @@ begin
end
if
;
end
if
;
end
process
;
end
process
;
tx_busy
<=
'1'
when
(
fifo_empty
=
'0'
)
or
(
tx_state
/=
TX_COMMA_IDLE
)
else
'0'
;
tx_busy
<=
'1'
when
(
fifo_empty
=
'0'
)
or
(
tx_state
/=
TX_COMMA_IDLE
)
else
'0'
;
pcs_dreq_o
<=
not
fifo_almost_full
;
pcs_dreq_o
<=
not
fifo_almost_full
;
end
behavioral
;
end
behavioral
;
...
...
modules/wr_endpoint/ep_wishbone_controller.vhd
View file @
1ef9c93f
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : ep_wishbone_controller.vhd
-- File : ep_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
-- Created : Sun
Nov 6 00:20:16
2011
-- Created : Sun
Oct 30 00:20:59
2011
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
...
...
modules/wr_endpoint/wr_endpoint.vhd
View file @
1ef9c93f
This diff is collapsed.
Click to expand it.
modules/wr_endpoint/wr_fabric_pkg.vhd
deleted
100644 → 0
View file @
191b4640
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
package
wr_fabric_pkg
is
constant
c_WRF_DATA
:
std_logic_vector
(
1
downto
0
)
:
=
"00"
;
constant
c_WRF_OOB
:
std_logic_vector
(
1
downto
0
)
:
=
"01"
;
constant
c_WRF_STATUS
:
std_logic_vector
(
1
downto
0
)
:
=
"10"
;
constant
c_WRF_USER
:
std_logic_vector
(
1
downto
0
)
:
=
"11"
;
constant
c_WRF_OOB_TYPE_RX
:
std_logic_vector
(
3
downto
0
)
:
=
"0000"
;
constant
c_WRF_OOB_TYPE_TX
:
std_logic_vector
(
3
downto
0
)
:
=
"0001"
;
type
t_wrf_status_reg
is
record
is_hp
:
std_logic
;
has_smac
:
std_logic
;
has_crc
:
std_logic
;
error
:
std_logic
;
tag_me
:
std_logic
;
match_class
:
std_logic_vector
(
7
downto
0
);
end
record
;
type
t_wrf_source_out
is
record
adr
:
std_logic_vector
(
1
downto
0
);
dat
:
std_logic_vector
(
15
downto
0
);
cyc
:
std_logic
;
stb
:
std_logic
;
we
:
std_logic
;
sel
:
std_logic_vector
(
1
downto
0
);
end
record
;
type
t_wrf_source_in
is
record
ack
:
std_logic
;
stall
:
std_logic
;
err
:
std_logic
;
rty
:
std_logic
;
end
record
;
type
t_wrf_oob
is
record
valid
:
std_logic
;
oob_type
:
std_logic_vector
(
3
downto
0
);
ts_r
:
std_logic_vector
(
27
downto
0
);
ts_f
:
std_logic_vector
(
3
downto
0
);
frame_id
:
std_logic_vector
(
15
downto
0
);
port_id
:
std_logic_vector
(
5
downto
0
);
end
record
;
subtype
t_wrf_sink_in
is
t_wrf_source_out
;
subtype
t_wrf_sink_out
is
t_wrf_source_in
;
function
f_marshall_wrf_status
(
stat
:
t_wrf_status_reg
)
return
std_logic_vector
;
function
f_unmarshall_wrf_status
(
stat
:
std_logic_vector
)
return
t_wrf_status_reg
;
constant
c_dummy_src_in
:
t_wrf_source_in
:
=
(
'0'
,
'0'
,
'0'
,
'0'
);
constant
c_dummy_snk_in
:
t_wrf_sink_in
:
=
((
others
=>
'X'
),
(
others
=>
'X'
),
'0'
,
'0'
,
'X'
,
(
others
=>
'X'
));
end
wr_fabric_pkg
;
package
body
wr_fabric_pkg
is
function
f_marshall_wrf_status
(
stat
:
t_wrf_status_reg
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
15
downto
0
);
begin
tmp
(
0
)
:
=
stat
.
is_hp
;
tmp
(
1
)
:
=
stat
.
error
;
tmp
(
2
)
:
=
stat
.
has_smac
;
tmp
(
3
)
:
=
stat
.
has_crc
;
tmp
(
15
downto
8
)
:
=
stat
.
match_class
;
return
tmp
;
end
function
;
function
f_unmarshall_wrf_status
(
stat
:
std_logic_vector
)
return
t_wrf_status_reg
is
variable
tmp
:
t_wrf_status_reg
;
begin
tmp
.
is_hp
:
=
stat
(
0
);
tmp
.
error
:
=
stat
(
1
);
tmp
.
has_smac
:
=
stat
(
2
);
tmp
.
has_crc
:
=
stat
(
3
);
tmp
.
match_class
:
=
stat
(
15
downto
8
);
return
tmp
;
end
function
;
end
wr_fabric_pkg
;
modules/wr_endpoint/xwr_endpoint.vhd
View file @
1ef9c93f
...
@@ -6,7 +6,7 @@
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Company : CERN BE-Co-HT
-- Created : 2010-04-26
-- Created : 2010-04-26
-- Last update: 201
1-10-30
-- Last update: 201
2-01-23
-- Platform : FPGA-generics
-- Platform : FPGA-generics
-- Standard : VHDL
-- Standard : VHDL
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
...
@@ -32,6 +32,7 @@ entity xwr_endpoint is
...
@@ -32,6 +32,7 @@ entity xwr_endpoint is
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_simulation
:
boolean
:
=
false
;
g_simulation
:
boolean
:
=
false
;
g_tx_force_gap_length
:
integer
:
=
0
;
g_pcs_16bit
:
boolean
:
=
false
;
g_pcs_16bit
:
boolean
:
=
false
;
g_rx_buffer_size
:
integer
:
=
1024
;
g_rx_buffer_size
:
integer
:
=
1024
;
g_with_rx_buffer
:
boolean
:
=
true
;
g_with_rx_buffer
:
boolean
:
=
true
;
...
@@ -54,7 +55,7 @@ entity xwr_endpoint is
...
@@ -54,7 +55,7 @@ entity xwr_endpoint is
-- reference clock / 2 (62.5 MHz, in-phase with refclk)
-- reference clock / 2 (62.5 MHz, in-phase with refclk)
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
;
-- sync reset (clk_sys_i domain), active LO
-- sync reset (clk_sys_i domain), active LO
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
@@ -182,6 +183,7 @@ begin
...
@@ -182,6 +183,7 @@ begin
generic
map
(
generic
map
(
g_interface_mode
=>
g_interface_mode
,
g_interface_mode
=>
g_interface_mode
,
g_address_granularity
=>
g_address_granularity
,
g_address_granularity
=>
g_address_granularity
,
g_tx_force_gap_length
=>
g_tx_force_gap_length
,
g_simulation
=>
g_simulation
,
g_simulation
=>
g_simulation
,
g_pcs_16bit
=>
g_pcs_16bit
,
g_pcs_16bit
=>
g_pcs_16bit
,
...
@@ -262,6 +264,7 @@ begin
...
@@ -262,6 +264,7 @@ begin
wb_dat_i
=>
wb_i
.
dat
,
wb_dat_i
=>
wb_i
.
dat
,
wb_dat_o
=>
wb_o
.
dat
,
wb_dat_o
=>
wb_o
.
dat
,
wb_ack_o
=>
wb_o
.
ack
,
wb_ack_o
=>
wb_o
.
ack
,
wb_stall_o
=>
wb_o
.
stall
,
led_link_o
=>
led_link_o
,
led_link_o
=>
led_link_o
,
led_act_o
=>
led_act_o
);
led_act_o
=>
led_act_o
);
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment