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Commit 1e1ca8df authored by Maciej Lipinski's avatar Maciej Lipinski
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imported xwr_transmission stuff from Btrain repo to wr-cores 

- xwr_transmission is a container for rx and tx streamers that might be
  generally useful in non-Btrain projects. it was initially developed
  for Btrain
- it was imported from the following repo/branch/commit
  ssh://git@gitlab.cern.ch:7999/BTrain-TEAM/PS-BTrain-over-WhiteRabbit.git
  ML-addressReviewFeedback
  cfc0fc0eeb1f81f80154a2a30027c1e6df5d0171
- it was imported with history following steps in:
  http://stackoverflow.com/questions/1365541/how-to-move-files-from-one-git-repo-to-another-not-a-clone-preserving-history
parents 2e23cac3 59536ce9
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modules/wr_streamers/Manifest.py
View file @ 1e1ca8df
......@@ -6,4 +6,8 @@ files = ["streamers_pkg.vhd",
"rx_streamer.vhd",
"gc_escape_inserter.vhd",
"gc_escape_detector.vhd",
"dropping_buffer.vhd"]
"dropping_buffer.vhd",
"wr_transmission_wbgen2_pkg.vhd",
"xwr_transmission.vhd",
"wr_transmission_pkg.vhd",
"wr_transmission_wb.vhd"]
modules/wr_streamers/build_wb.sh 0 → 100755
View file @ 1e1ca8df
#!/bin/bash
wbgen2 -D ../../../doc/wb-regs/wr_transmission_wb.html -p wr_transmission_wbgen2_pkg.vhd -H record -V wr_transmission_wb.vhd --cstyle defines --lang vhdl -K ../../testbench/include/regs/wr_transmission_wb.svh wr_transmission_wb.wb
\ No newline at end of file
modules/wr_streamers/wr_transmission_pkg.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Title : Btrain over White Rabbit
-- Project : Btrain
-------------------------------------------------------------------------------
-- File : BtrainFMC_pkg.vhd
-- Author : Maciej Lipinski
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
--
-- package to be called where xwr_transmission is used. Important
-- part of the package are the two constants that provide information about
-- the generic array size - this array is used to provide information about
-- statistics to the WRPC
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2016 CERN/BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-30 1.0 mlipinsk Created
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all; -- needed for t_wishbone_slave_in, etc
use work.streamers_pkg.all; -- needed for streamers
use work.wr_fabric_pkg.all; -- neede for :t_wrf_source_in, etc
use work.wrcore_pkg.all; -- needed for t_generic_word_array
use work.wr_transmission_wbgen2_pkg.all;
package wr_transmission_pkg is
constant c_WR_TRANS_ARR_SIZE_OUT : integer := c_STREAMERS_ARR_SIZE_OUT+3;
constant c_WR_TRANS_ARR_SIZE_IN : integer := c_STREAMERS_ARR_SIZE_IN;
component xwr_transmission is
generic (
g_data_width : integer := 32
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
tx_data_i : in std_logic_vector(g_data_width-1 downto 0);
tx_valid_i : in std_logic;
tx_dreq_o : out std_logic;
tx_last_p1_i : in std_logic := '1';
tx_flush_p1_i : in std_logic := '0';
rx_first_p1_o : out std_logic;
rx_last_p1_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_dreq_i : in std_logic;
clk_ref_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out;
snmp_array_o : out t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
snmp_array_i : in t_generic_word_array(c_WR_TRANS_ARR_SIZE_IN -1 downto 0)
);
end component;
end package;
modules/wr_streamers/wr_transmission_wb.vhd 0 → 100644
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This diff is collapsed.
modules/wr_streamers/wr_transmission_wb.wb 0 → 100644
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-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Transmission control and debug";
description = "\
-----------------------------------------------------------------\
This WB registers allow to diagnose transmission and reception of\
data using WR streamers. \
In particular, these registers provide access to streamer's \
statistics that can be also access from SNMP, if supported. \
-----------------------------------------------------------------\
Copyright (c) 2016 CERN/BE-CO-HT & CERN/TE-MS-MM \
\
This source file is free software; you can redistribute it \
and/or modify it under the terms of the GNU Lesser General \
Public License as published by the Free Software Foundation; \
either version 2.1 of the License, or (at your option) any \
later version. \
\
This source is distributed in the hope that it will be \
useful, but WITHOUT ANY WARRANTY; without even the implied \
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \
PURPOSE. See the GNU Lesser General Public License for more \
details \
\
You should have received a copy of the GNU Lesser General \
Public License along with this source; if not, download it \
from http://www.gnu.org/licenses/lgpl-2.1.html \
-----------------------------------------------------------------";
prefix = "wr_transmission";
hdl_entity = "wr_transmission_wb";
reg {
name = "Statistics status and ctrl register";
prefix = "SSCR1";
field {
name = "Reset statistics";
prefix = "RST_STATS";
description = "Writing 1 reset counters, latency acc/max/min. This reset is timestamped";
type = MONOSTABLE;
};
field {
name = "Reset tx seq id";
prefix = "RST_SEQ_ID";
description = "Writing 1 reset sequence ID of transmitted frames";
type = MONOSTABLE;
};
field {
name = "Snapshot statistics";
prefix = "SNAPSHOT_STATS";
description = "Writing 1 snapshots statistics for reading, it means that all the counters \
are copied at the same instant to registers and this registers can be read\
via wishbone/snmp while the counters are still running in the background. \
this allows to read coherent data";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Latency accumulator overflow";
prefix = "RX_LATENCY_ACC_OVERFLOW";
description = "Latency accumulator overflow - the lateny accumulator value is invalid";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reset timestamp cycles";
prefix = "RST_TS_CYC";
description = "Timestamp of the last reset of stats (RST_STAT) -- count of clock cycles";
type = SLV;
size = 28;
align = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Statistics status and ctrl register";
prefix = "SSCR2";
field {
name = "Reset timestamp 32 LSB of TAI";
prefix = "RST_TS_TAI_LSB";
description = "Timestamp of the last reset of stats (RST_STAT) -- LSB 32 bits of TAI";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Tx statistics";
prefix = "TX_STAT";
field {
name = "WR Streamer frame sent count";
description = "Number of sent wr streamer frames since reset";
prefix = "TX_SENT_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT1";
field {
name = "WR Streamer frame received count";
description = "Number of received wr streamer frames since reset";
prefix = "RX_RCVD_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT2";
field {
name = "WR Streamer frame loss count";
description = "Number of lost wr streamer frames since reset";
prefix = "RX_LOSS_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT3";
field {
name = "WR Streamer frame latency";
description = "Maximum latency of received frames since reset";
prefix = "RX_LATENCY_MAX";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT4";
field {
name = "WR Streamer frame latency";
description = "Minimum latency of received frames since reset";
prefix = "RX_LATENCY_MIN";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT5";
field {
name = "WR Streamer frame latency";
description = "Accumulated latency (LSB) of received frames since reset";
prefix = "RX_LATENCY_ACC_LSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT6";
field {
name = "WR Streamer frame latency";
description = "Accumulated latency (MSB) of received frames since reset";
prefix = "RX_LATENCY_ACC_MSB";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT7";
field {
name = "WR Streamer frame latency counter";
description = "Counter of the accumulated frequency (so avg can be calculated in SW) since reset";
prefix = "RX_LATENCY_ACC_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT8";
field {
name = "WR Streamer block loss count";
description = "Number of indications that one or more blocks in a frame were lost (probably CRC\
error) since reset";
prefix = "RX_LOST_BLOCK_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "DBG Control register";
prefix = "DBG_CTRL";
description = "This register is meant to control simple debugging of transmitted or received data.\
It allows to sniff a 32-bit word at a configurable offset from received or transmitted data.";
field {
name = "Debug Tx (0) or Rx (1)";
prefix = "MUX";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Debug Start byte";
prefix = "START_BYTE";
description ="The offset, in bytes, from which the 32-bit word is read.";
type = SLV;
align =8;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DBG Data";
prefix = "DBG_DATA";
field {
name = "Debug content";
size = 32;
type =SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "DBG RX_BVALUE";
prefix = "DBG_RX_BVALUE";
field {
name = "Debug content";
size = 32;
type =SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "DBG tx bvalue";
prefix = "DBG_TX_BVALUE";
field {
name = "Debug content";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Test value";
prefix = "DUMMY";
field {
name = "DUMMY value to read";
prefix = "DUMMY";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd 0 → 100644
View file @ 1e1ca8df
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Transmission control and debug
---------------------------------------------------------------------------------------
-- File : wr_transmission_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created : Thu Jul 28 16:59:59 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wr_transmission_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_wr_transmission_in_registers is record
sscr1_rx_latency_acc_overflow_i : std_logic;
sscr1_rst_ts_cyc_i : std_logic_vector(27 downto 0);
sscr2_rst_ts_tai_lsb_i : std_logic_vector(31 downto 0);
tx_stat_tx_sent_cnt_i : std_logic_vector(31 downto 0);
rx_stat1_rx_rcvd_cnt_i : std_logic_vector(31 downto 0);
rx_stat2_rx_loss_cnt_i : std_logic_vector(31 downto 0);
rx_stat3_rx_latency_max_i : std_logic_vector(27 downto 0);
rx_stat4_rx_latency_min_i : std_logic_vector(27 downto 0);
rx_stat5_rx_latency_acc_lsb_i : std_logic_vector(31 downto 0);
rx_stat6_rx_latency_acc_msb_i : std_logic_vector(31 downto 0);
rx_stat7_rx_latency_acc_cnt_i : std_logic_vector(31 downto 0);
rx_stat8_rx_lost_block_cnt_i : std_logic_vector(31 downto 0);
dbg_data_i : std_logic_vector(31 downto 0);
dbg_rx_bvalue_i : std_logic_vector(31 downto 0);
dbg_tx_bvalue_i : std_logic_vector(31 downto 0);
dummy_dummy_i : std_logic_vector(31 downto 0);
end record;
constant c_wr_transmission_in_registers_init_value: t_wr_transmission_in_registers := (
sscr1_rx_latency_acc_overflow_i => '0',
sscr1_rst_ts_cyc_i => (others => '0'),
sscr2_rst_ts_tai_lsb_i => (others => '0'),
tx_stat_tx_sent_cnt_i => (others => '0'),
rx_stat1_rx_rcvd_cnt_i => (others => '0'),
rx_stat2_rx_loss_cnt_i => (others => '0'),
rx_stat3_rx_latency_max_i => (others => '0'),
rx_stat4_rx_latency_min_i => (others => '0'),
rx_stat5_rx_latency_acc_lsb_i => (others => '0'),
rx_stat6_rx_latency_acc_msb_i => (others => '0'),
rx_stat7_rx_latency_acc_cnt_i => (others => '0'),
rx_stat8_rx_lost_block_cnt_i => (others => '0'),
dbg_data_i => (others => '0'),
dbg_rx_bvalue_i => (others => '0'),
dbg_tx_bvalue_i => (others => '0'),
dummy_dummy_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_wr_transmission_out_registers is record
sscr1_rst_stats_o : std_logic;
sscr1_rst_seq_id_o : std_logic;
sscr1_snapshot_stats_o : std_logic;
dbg_ctrl_mux_o : std_logic;
dbg_ctrl_start_byte_o : std_logic_vector(7 downto 0);
end record;
constant c_wr_transmission_out_registers_init_value: t_wr_transmission_out_registers := (
sscr1_rst_stats_o => '0',
sscr1_rst_seq_id_o => '0',
sscr1_snapshot_stats_o => '0',
dbg_ctrl_mux_o => '0',
dbg_ctrl_start_byte_o => (others => '0')
);
function "or" (left, right: t_wr_transmission_in_registers) return t_wr_transmission_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body wr_transmission_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_wr_transmission_in_registers) return t_wr_transmission_in_registers is
variable tmp: t_wr_transmission_in_registers;
begin
tmp.sscr1_rx_latency_acc_overflow_i := f_x_to_zero(left.sscr1_rx_latency_acc_overflow_i) or f_x_to_zero(right.sscr1_rx_latency_acc_overflow_i);
tmp.sscr1_rst_ts_cyc_i := f_x_to_zero(left.sscr1_rst_ts_cyc_i) or f_x_to_zero(right.sscr1_rst_ts_cyc_i);
tmp.sscr2_rst_ts_tai_lsb_i := f_x_to_zero(left.sscr2_rst_ts_tai_lsb_i) or f_x_to_zero(right.sscr2_rst_ts_tai_lsb_i);
tmp.tx_stat_tx_sent_cnt_i := f_x_to_zero(left.tx_stat_tx_sent_cnt_i) or f_x_to_zero(right.tx_stat_tx_sent_cnt_i);
tmp.rx_stat1_rx_rcvd_cnt_i := f_x_to_zero(left.rx_stat1_rx_rcvd_cnt_i) or f_x_to_zero(right.rx_stat1_rx_rcvd_cnt_i);
tmp.rx_stat2_rx_loss_cnt_i := f_x_to_zero(left.rx_stat2_rx_loss_cnt_i) or f_x_to_zero(right.rx_stat2_rx_loss_cnt_i);
tmp.rx_stat3_rx_latency_max_i := f_x_to_zero(left.rx_stat3_rx_latency_max_i) or f_x_to_zero(right.rx_stat3_rx_latency_max_i);
tmp.rx_stat4_rx_latency_min_i := f_x_to_zero(left.rx_stat4_rx_latency_min_i) or f_x_to_zero(right.rx_stat4_rx_latency_min_i);
tmp.rx_stat5_rx_latency_acc_lsb_i := f_x_to_zero(left.rx_stat5_rx_latency_acc_lsb_i) or f_x_to_zero(right.rx_stat5_rx_latency_acc_lsb_i);
tmp.rx_stat6_rx_latency_acc_msb_i := f_x_to_zero(left.rx_stat6_rx_latency_acc_msb_i) or f_x_to_zero(right.rx_stat6_rx_latency_acc_msb_i);
tmp.rx_stat7_rx_latency_acc_cnt_i := f_x_to_zero(left.rx_stat7_rx_latency_acc_cnt_i) or f_x_to_zero(right.rx_stat7_rx_latency_acc_cnt_i);
tmp.rx_stat8_rx_lost_block_cnt_i := f_x_to_zero(left.rx_stat8_rx_lost_block_cnt_i) or f_x_to_zero(right.rx_stat8_rx_lost_block_cnt_i);
tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
tmp.dbg_rx_bvalue_i := f_x_to_zero(left.dbg_rx_bvalue_i) or f_x_to_zero(right.dbg_rx_bvalue_i);
tmp.dbg_tx_bvalue_i := f_x_to_zero(left.dbg_tx_bvalue_i) or f_x_to_zero(right.dbg_tx_bvalue_i);
tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
return tmp;
end function;
end package body;
modules/wr_streamers/xwr_transmission.vhd 0 → 100644
View file @ 1e1ca8df
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