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White Rabbit core collection
Commit 1daada1a authored by Maciej Lipinski's avatar Maciej Lipinski
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updated wr transmission to include the new counting of separately lost frames and blocks

parent 1bc23230
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Showing with 38 additions and 7 deletions
wr_transmission_wb.vhd
View file @ 1daada1a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_transmission_wb.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created : Wed Jun 8 12:06:08 2016
-- Created : Fri Jun 10 18:36:57 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
......@@ -158,6 +158,12 @@ begin
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat8_rx_lost_block_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
wr_transmission_dbg_ctrl_mux_int <= wrdata_reg(0);
wr_transmission_dbg_ctrl_start_byte_int <= wrdata_reg(15 downto 8);
......@@ -189,13 +195,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
when "1100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dbg_data_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
when "1101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dummy_dummy_i;
......@@ -238,6 +244,7 @@ begin
-- WR Streamer frame latency
-- WR Streamer frame latency
-- WR Streamer frame latency counter
-- WR Streamer block loss count
-- Debug Tx or Rx
regs_o.dbg_ctrl_mux_o <= wr_transmission_dbg_ctrl_mux_int;
-- Debug Start byte
......
wr_transmission_wb.wb
View file @ 1daada1a
......@@ -153,6 +153,20 @@ peripheral {
access_dev = WRITE_ONLY;
};
};
reg {
name = "Rx statistics";
prefix = "RX_STAT8";
field {
name = "WR Streamer block loss count";
description = "Number of indications that one or more blocks in a frame were lost (probably CRC\
error, since reset";
prefix = "RX_LOST_BLOCK_CNT";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "DBG Control register";
prefix = "DBG_CTRL";
......
wr_transmission_wbgen2_pkg.vhd
View file @ 1daada1a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_transmission_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_transmission_wb.wb
-- Created : Wed Jun 8 12:06:08 2016
-- Created : Fri Jun 10 18:36:57 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_transmission_wb.wb
......@@ -31,6 +31,7 @@ package wr_transmission_wbgen2_pkg is
rx_stat5_rx_latency_acc_lsb_i : std_logic_vector(31 downto 0);
rx_stat6_rx_latency_acc_msb_i : std_logic_vector(31 downto 0);
rx_stat7_rx_latency_acc_cnt_i : std_logic_vector(31 downto 0);
rx_stat8_rx_lost_block_cnt_i : std_logic_vector(31 downto 0);
dbg_data_i : std_logic_vector(31 downto 0);
dummy_dummy_i : std_logic_vector(31 downto 0);
end record;
......@@ -47,6 +48,7 @@ package wr_transmission_wbgen2_pkg is
rx_stat5_rx_latency_acc_lsb_i => (others => '0'),
rx_stat6_rx_latency_acc_msb_i => (others => '0'),
rx_stat7_rx_latency_acc_cnt_i => (others => '0'),
rx_stat8_rx_lost_block_cnt_i => (others => '0'),
dbg_data_i => (others => '0'),
dummy_dummy_i => (others => '0')
);
......@@ -104,6 +106,7 @@ tmp.rx_stat4_rx_latency_min_i := f_x_to_zero(left.rx_stat4_rx_latency_min_i) or
tmp.rx_stat5_rx_latency_acc_lsb_i := f_x_to_zero(left.rx_stat5_rx_latency_acc_lsb_i) or f_x_to_zero(right.rx_stat5_rx_latency_acc_lsb_i);
tmp.rx_stat6_rx_latency_acc_msb_i := f_x_to_zero(left.rx_stat6_rx_latency_acc_msb_i) or f_x_to_zero(right.rx_stat6_rx_latency_acc_msb_i);
tmp.rx_stat7_rx_latency_acc_cnt_i := f_x_to_zero(left.rx_stat7_rx_latency_acc_cnt_i) or f_x_to_zero(right.rx_stat7_rx_latency_acc_cnt_i);
tmp.rx_stat8_rx_lost_block_cnt_i := f_x_to_zero(left.rx_stat8_rx_lost_block_cnt_i) or f_x_to_zero(right.rx_stat8_rx_lost_block_cnt_i);
tmp.dbg_data_i := f_x_to_zero(left.dbg_data_i) or f_x_to_zero(right.dbg_data_i);
tmp.dummy_dummy_i := f_x_to_zero(left.dummy_dummy_i) or f_x_to_zero(right.dummy_dummy_i);
return tmp;
......
xwr_transmission.vhd
View file @ 1daada1a
......@@ -154,12 +154,14 @@ architecture rtl of xwr_transmission is
signal wb_regs_slave_out : t_wishbone_slave_out;
signal rx_latency_valid : std_logic;
signal rx_latency : std_logic_vector(27 downto 0);
signal rx_lost : std_logic;
signal rx_lost_frames : std_logic;
signal rx_lost_blocks : std_logic;
signal rx_frame : std_logic;
signal tx_frame : std_logic;
signal reset_time_tai : std_logic_vector(39 downto 0);
signal latency_acc : std_logic_vector(63 downto 0);
signal rx_valid : std_logic;
signal rx_lost_frames_cnt : std_logic_vector(14 downto 0);
function f_dbg_word_starting_at_byte(data_in, start_bit : std_logic_vector) return std_logic_vector is
variable sb : integer := 0;
variable result : std_logic_vector(31 downto 0);
......@@ -220,7 +222,9 @@ begin
rx_data_o => rx_data,
rx_valid_o => rx_valid,
rx_dreq_i => rx_dreq_i,
rx_lost_o => rx_lost,
rx_lost_o => rx_lost_blocks,
rx_lost_frames_o => rx_lost_frames,
rx_lost_frames_cnt_o => rx_lost_frames_cnt,
rx_latency_o => rx_latency,
rx_latency_valid_o => rx_latency_valid,
rx_frame_o => rx_frame,
......@@ -242,7 +246,9 @@ begin
rst_n_i => rst_n_i,
sent_frame_i => tx_frame,
rcvd_frame_i => rx_frame,
lost_frame_i => rx_lost,
lost_frame_i => rx_lost_frames,
lost_block_i => rx_lost_blocks,
lost_frames_cnt_i => rx_lost_frames_cnt,
rcvd_latency_i => rx_latency,
rcvd_latency_valid_i => rx_latency_valid,
tm_time_valid_i => tm_time_valid_i,
......@@ -254,6 +260,7 @@ begin
sent_frame_cnt_o => regs_to_wb.tx_stat_tx_sent_cnt_i,
rcvd_frame_cnt_o => regs_to_wb.rx_stat1_rx_rcvd_cnt_i,
lost_frame_cnt_o => regs_to_wb.rx_stat2_rx_loss_cnt_i,
lost_block_cnt_o => regs_to_wb.rx_stat8_rx_lost_block_cnt_i,
latency_cnt_o => regs_to_wb.rx_stat7_rx_latency_acc_cnt_i,
latency_acc_o => latency_acc,
latency_max_o => regs_to_wb.rx_stat3_rx_latency_max_i,
......
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