Commit 1c53def3 authored by Maciej Lipinski's avatar Maciej Lipinski

Merge branch 'Fixed-latency-streamers' into proposed_master

parents 94c94685 8c3ee07c
......@@ -75,6 +75,10 @@ package wr_board_pkg is
application_size : integer
) return integer;
function f_pick_clk_ref_rate (
pcs_16bit_in : boolean
) return integer;
function f_vectorize_diag (
diag_in : t_generic_word_array;
diag_vector_size : integer)
......@@ -288,6 +292,18 @@ package body wr_board_pkg is
end if;
end f_pick_diag_size;
-- guess clk_ref (WR reference Clock) rate based on PCS word width
function f_pick_clk_ref_rate (
pcs_16bit_in : boolean
) return integer is
begin
if(pcs_16bit_in = TRUE) then
return 62500000;
else
return 125000000;
end if;
end f_pick_clk_ref_rate;
function f_vectorize_diag (
diag_in : t_generic_word_array;
diag_vector_size : integer)
......
......@@ -491,7 +491,8 @@ begin -- architecture struct
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_simulation => g_simulation)
g_simulation => g_simulation,
g_clk_ref_rate => f_pick_clk_ref_rate(g_pcs_16bit))
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......
Subproject commit 4e5f7badf0b72f51bdb01c63fcdc6d69afb4b750
Subproject commit f73bc3d2959bdaab52adf910d99ed90cabab11ab
......@@ -4,5 +4,6 @@ files = ["dmtd_phase_meas.vhd",
"hpll_period_detect.vhd",
"pulse_gen.vhd",
"oserdes_4_to_1.vhd",
"pulse_stamper.vhd" ]
"pulse_stamper.vhd",
"pulse_stamper_sync.vhd"]
......@@ -84,6 +84,31 @@ architecture rtl of pulse_stamper is
signal pulse_sys_p1 : std_logic;
signal pulse_back : std_logic_vector(2 downto 0);
-- One of two clocks is used in WR for timestamping: 125MHz or 62.5MHz
-- This functions translates the cycle count into 125MHz-clock cycles
-- in the case when 62.5MHz clock is used. As a result, timestamps are
-- always in the same "clock domain". This is important, e.g. for streamers,
-- in applicatinos where one WR Node works with 62.5MHz WR clock and
-- another in 125MHz.
function f_8ns_cycle_cnt (in_cyc: std_logic_vector; ref_clk: integer)
return std_logic_vector is
variable out_cyc : std_logic_vector(27 downto 0);
begin
if (ref_clk = 125000000) then
out_cyc := in_cyc;
elsif(ref_clk = 62500000) then
out_cyc := in_cyc(26 downto 0) & '0';
else
assert FALSE report
"The only ref_clk_rate supported: 62.5MHz and 125MHz"
severity FAILURE;
end if;
return out_cyc;
end f_8ns_cycle_cnt;
begin -- architecture rtl
-- Synchronization of external pulse into the clk_ref_i clock domain
......@@ -150,7 +175,7 @@ begin -- architecture rtl
tag_valid_o <= '0';
elsif pulse_sys_p1='1' then
tag_tai_o <= tag_utc_ref;
tag_cycles_o <= tag_cycles_ref;
tag_cycles_o <= f_8ns_cycle_cnt(tag_cycles_ref,g_ref_clk_rate);
tag_valid_o <= '1';
else
tag_valid_o <='0';
......
--------------------------------------------------------------------------------
-- CERN
-- wr-cores/timing
-- https://www.ohwr.org/project/wr-cores
--------------------------------------------------------------------------------
--
-- unit name : pulse_stamper_sync.vhd
-- author : Tomasz Wlostowski, based on pulse_stamper by Javier Serrano
-- description:
--
-- this module allows to time stamp pulses that are synchronous to clk_ref
-- domain, so in the domain of the WR time (i.e. tm_tai_i and tm_cycles_i).
-- The generated timestamp is then made available in the clk_sys domain.
--
--------------------------------------------------------------------------------
-- Copyright (c) 2019 CERN BE/CO/HT
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity pulse_stamper_sync is
generic (
-- reference clock frequency
g_ref_clk_rate : integer := 125000000);
port(
clk_ref_i : in std_logic; -- timing reference clock
clk_sys_i : in std_logic; -- data output reference clock
rst_n_i : in std_logic; -- system reset
pulse_i : in std_logic; -- pulse to be stamped (ref clock domain)
-------------------------------------------------------------------------------
-- Timing input (from WRPC), clk_ref_i domain
------------------------------------------------------------------------------
-- 1: time given on tm_utc_i and tm_cycles_i is valid (otherwise, don't timestamp)
tm_time_valid_i : in std_logic;
-- number of seconds
tm_tai_i : in std_logic_vector(39 downto 0);
-- number of clk_ref_i cycles
tm_cycles_i : in std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Time tag output (clk_sys_i domain)
---------------------------------------------------------------------------
tag_tai_o : out std_logic_vector(39 downto 0);
tag_cycles_o : out std_logic_vector(27 downto 0);
-- single-cycle pulse: strobe tag on tag_utc_o and tag_cycles_o
tag_valid_o : out std_logic;
tag_error_o : out std_logic -- 1 when pulse came with tm_time_valid_i = 0
);
end pulse_stamper_sync;
architecture rtl of pulse_stamper_sync is
signal rst_n_ref : std_logic;
signal pulse_d : std_logic;
signal tag_ready_ref, tag_ready_ref_d, tag_ready_ref_p1 : std_logic;
signal tag_time_valid_ref : std_logic;
signal tag_ready_sys_p1 : std_logic;
-- Time tagger signals
signal tag_utc_ref : std_logic_vector(39 downto 0);
signal tag_cycles_ref : std_logic_vector(27 downto 0);
-- One of two clocks is used in WR for timestamping: 125MHz or 62.5MHz
-- This functions translates the cycle count into 125MHz-clock cycles
-- in the case when 62.5MHz clock is used. As a result, timestamps are
-- always in the same "clock domain". This is important, e.g. for streamers,
-- in applicatinos where one WR Node works with 62.5MHz WR clock and
-- another in 125MHz.
function f_8ns_cycle_cnt (in_cyc : std_logic_vector; ref_clk : integer)
return std_logic_vector is
variable out_cyc : std_logic_vector(27 downto 0);
begin
if (ref_clk = 125000000) then
out_cyc := in_cyc;
elsif(ref_clk = 62500000) then
out_cyc := in_cyc(26 downto 0) & '0';
else
assert false report
"The only ref_clk_rate supported: 62.5MHz and 125MHz"
severity failure;
end if;
return out_cyc;
end f_8ns_cycle_cnt;
begin -- architecture rtl
U_sync_reset_ref : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_n_ref);
-- Time tagging of the pulse, still in the clk_ref_i domain
p_tagger : process (clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if rst_n_ref = '0' then
pulse_d <= '0';
tag_ready_ref <= '0';
tag_ready_ref_d <= '0';
tag_ready_ref_p1 <= '0';
else
pulse_d <= pulse_i;
tag_ready_ref_d <= tag_ready_ref;
tag_ready_ref_p1 <= not tag_ready_ref_d and tag_ready_ref;
if pulse_i = '1' and pulse_d = '0' then
tag_utc_ref <= tm_tai_i;
tag_cycles_ref <= tm_cycles_i;
tag_time_valid_ref <= tm_time_valid_i;
tag_ready_ref <= '1';
else
tag_ready_ref <= '0';
end if;
end if;
end if;
end process;
U_SyncTagReady : gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_i,
rst_in_n_i => rst_n_ref,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_i,
d_ready_o => open,
d_p_i => tag_ready_ref_p1,
q_p_o => tag_ready_sys_p1);
-- Now we can take the time tags into the clk_sys_i domain
p_sys_tags : process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
tag_tai_o <= (others => '0');
tag_cycles_o <= (others => '0');
tag_valid_o <= '0';
tag_error_o <= '0';
elsif tag_ready_sys_p1 = '1' then
tag_tai_o <= tag_utc_ref;
tag_cycles_o <= f_8ns_cycle_cnt(tag_cycles_ref, g_ref_clk_rate);
tag_valid_o <= '1';
tag_error_o <= not tag_time_valid_ref;
else
tag_valid_o <= '0';
end if;
end if;
end process;
end architecture rtl;
......@@ -93,7 +93,7 @@ architecture behavioral of ep_rx_crc_size_check is
signal crc_gen_enable : std_logic;
signal crc_gen_reset : std_logic;
signal crc_match, crc_match2 : std_logic;
signal crc_match : std_logic;
signal crc_cur : std_logic_vector(31 downto 0);
signal crc_in_data : std_logic_vector(15 downto 0);
......@@ -106,7 +106,6 @@ architecture behavioral of ep_rx_crc_size_check is
signal state : t_state;
signal q_flush, q_empty : std_logic;
signal q_purge : std_logic;
signal q_in, q_out : std_logic_vector(17 downto 0);
signal q_bytesel : std_logic;
......@@ -306,6 +305,7 @@ begin -- behavioral
src_fab_o.error <= '1';
q_purge <= '1';
elsif(snk_fab_i.eof = '1') then
q_purge <= '1';
state <= ST_WAIT_FRAME;
else
state <= ST_OOB;
......@@ -324,6 +324,7 @@ begin -- behavioral
if(src_dreq_i = '1' and snk_fab_i.eof='1') then
state <= ST_WAIT_FRAME;
q_purge <= '1';
end if;
end case;
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2017-02-02
-- Last update: 2018-10-03
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -117,34 +117,6 @@ end ep_rx_path;
architecture behavioral of ep_rx_path is
type t_rx_deframer_state is (RXF_IDLE, RXF_DATA, RXF_FLUSH_STALL, RXF_FINISH_CYCLE, RXF_THROW_ERROR);
signal state : t_rx_deframer_state;
signal gap_cntr : unsigned(3 downto 0);
-- new sigs
signal counter : unsigned(7 downto 0);
signal rxdata_saved : std_logic_vector(15 downto 0);
signal next_hdr : std_logic;
signal is_pause : std_logic;
signal data_firstword : std_logic;
signal flush_stall : std_logic;
signal stb_int : std_logic;
signal fab_int : t_ep_internal_fabric;
signal dreq_int : std_logic;
signal ack_count : unsigned(7 downto 0);
signal src_out_int : t_wrf_source_out;
signal tmp_sel : std_logic;
signal tmp_dat : std_logic_vector(15 downto 0);
signal fab_pipe : t_fab_pipe(0 to 9);
signal dreq_pipe : std_logic_vector(9 downto 0);
......
......@@ -12,5 +12,9 @@ files = ["streamers_pkg.vhd",
"wr_streamers_wb.vhd",
"streamers_priv_pkg.vhd",
"xtx_streamers_stats.vhd",
"xrx_streamers_stats.vhd"
]
"xrx_streamers_stats.vhd",
"fixed_latency_delay.vhd",
"fixed_latency_ts_match.vhd",
"fifo_showahead_adapter.vhd",
"ts_restore_tai.vhd",
];
......@@ -58,7 +58,8 @@ entity dropping_buffer is
d_o : out std_logic_vector(g_data_width-1 downto 0);
d_valid_o : out std_logic;
d_req_i : in std_logic);
d_req_i : in std_logic;
d_full_o : out std_logic);
end dropping_buffer;
......@@ -104,6 +105,7 @@ begin -- behavioral
full <= '1' when (wr_ptr + 1 = rd_ptr) else '0';
d_req_o <= not full;
d_full_o <= full;
p_empty_reg : process(clk_i)
begin
......
--------------------------------------------------------------------------------
-- CERN
-- wr-cores/wr-streamers
-- https://www.ohwr.org/project/wr-cores
--------------------------------------------------------------------------------
--
-- unit name : fifo_showahead_adapter.vhd
-- author : Tomasz Wlostowski
-- description:
--
-- Emulation of show-ahead FIFO, used if the show-ahead feature in a FIFO
-- is not supported.
--
--
--------------------------------------------------------------------------------
-- Copyright (c) 2019 CERN BE/CO/HT
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity fifo_showahead_adapter is
generic (
g_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
fifo_q_i : in std_logic_vector(g_width-1 downto 0);
fifo_empty_i : in std_logic;
fifo_rd_o : out std_logic;
q_o : out std_logic_vector(g_width-1 downto 0);
valid_o : out std_logic;
rd_i : in std_logic
);
end fifo_showahead_adapter;
architecture rtl of fifo_showahead_adapter is
signal rd, rd_d : std_logic;
signal valid_int : std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_d <= '0';
valid_int <= '0';
else
rd_d <= rd;
if rd = '1' then
valid_int <= '1';
elsif rd_i = '1' then
valid_int <= not fifo_empty_i;
end if;
end if;
end if;
end process;
rd <= not fifo_empty_i when valid_int = '0' else rd_i and not fifo_empty_i;
q_o <= fifo_q_i;
fifo_rd_o <= rd;
valid_o <= valid_int;
end rtl;
This diff is collapsed.
This diff is collapsed.
......@@ -75,6 +75,11 @@ package streamers_pkg is
-- legacy: the streamers initially used in Btrain did not check/insert the escape
-- code. This is justified if only one block of a known number of words is sent/expected
escape_code_disable : boolean;
-- when non-zero, the datapath (tx port) are in the clk_ref_i clock
-- domain instead of clk_sys_i. This is a must for fixed latency mode if
-- clk_sys_i is asynchronous (i.e. not locked) to the WR timing.
use_ref_clk_for_data : integer;
end record;
-----------------------------------------------------------------------------------------
......@@ -105,6 +110,11 @@ package streamers_pkg is
-- In combination with the g_escape_code_disable generic set to TRUE, the behaviour of
-- the "Btrain streamers" can be recreated.
expected_words_number : integer;
-- when non-zero, the datapath (rx port) are in the clk_ref_i clock
-- domain instead of clk_sys_i. This is a must for fixed latency mode if
-- clk_sys_i is asynchronous (i.e. not locked) to the WR timing.
use_ref_clk_for_data : integer;
end record;
constant c_tx_streamer_params_defaut: t_tx_streamer_params :=(
......@@ -113,12 +123,14 @@ package streamers_pkg is
threshold => 128,
max_words_per_frame => 256,
timeout => 1024,
use_ref_clk_for_data => 0,
escape_code_disable => FALSE);
constant c_rx_streamer_params_defaut: t_rx_streamer_params :=(
data_width => 32,
buffer_size => 256,
escape_code_disable => FALSE,
use_ref_clk_for_data => 0,
expected_words_number => 0);
type t_rx_streamer_cfg is record
......@@ -139,6 +151,13 @@ package streamers_pkg is
filter_remote : std_logic;
-- value in cycles of fixed-latency enforced on data
fixed_latency : std_logic_vector(27 downto 0);
-- value in cycles of fixed-latency timeout (if it takes longer than this value
-- to output the packet, it's dropped)
fixed_latency_timeout : std_logic_vector(27 downto 0);
-- software controlled reset
sw_reset : std_logic;
end record;
type t_tx_streamer_cfg is record
......@@ -156,6 +175,8 @@ package streamers_pkg is
qtag_vid : std_logic_vector(11 downto 0);
-- priority used to tag
qtag_prio : std_logic_vector(2 downto 0);
-- software controlled reset
sw_reset : std_logic;
end record;
constant c_rx_streamer_cfg_default: t_rx_streamer_cfg :=(
......@@ -164,7 +185,9 @@ package streamers_pkg is
ethertype => x"dbff",
accept_broadcasts => '1',
filter_remote => '0',
fixed_latency => x"0000000");
fixed_latency => x"0000000",
fixed_latency_timeout => x"1000000",
sw_reset => '0');
constant c_tx_streamer_cfg_default: t_tx_streamer_cfg :=(
mac_local => x"000000000000",
......@@ -172,7 +195,8 @@ package streamers_pkg is
ethertype => x"dbff",
qtag_ena => '0',
qtag_vid => x"000",
qtag_prio => "000");
qtag_prio => "000",
sw_reset => '0');
component xtx_streamer
generic (
......@@ -183,13 +207,15 @@ package streamers_pkg is
g_tx_timeout : integer := 1024;
g_escape_code_disable : boolean := FALSE;
g_simulation : integer := 0;
g_sim_startup_cnt : integer := 6250);--100us
g_sim_startup_cnt : integer := 6250;--100us
g_clk_ref_rate : integer := 125000000;
g_use_ref_clock_for_data : integer := 0);
port (
clk_sys_i : in std_logic;
clk_ref_i : in std_logic := '0';
rst_n_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
clk_ref_i : in std_logic := '0';
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
tm_cycles_i : in std_logic_vector(27 downto 0) := x"0000000";
......@@ -209,7 +235,11 @@ package streamers_pkg is
g_data_width : integer := 32;
g_buffer_size : integer := 256;
g_escape_code_disable : boolean := FALSE;
g_expected_words_number : integer := 0);
g_expected_words_number : integer := 0;
g_clk_ref_rate : integer := 125000000;
g_simulation : integer := 0;
g_sim_cycle_counter_range : integer := 125000000;
g_use_ref_clock_for_data : integer := 0);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -223,6 +253,8 @@ package streamers_pkg is
rx_last_p1_o : out std_logic;
rx_data_o : out std_logic_vector(g_data_width-1 downto 0);
rx_valid_o : out std_logic;
rx_late_o : out std_logic;
rx_timeout_o : out std_logic;
rx_dreq_i : in std_logic;
rx_lost_p1_o : out std_logic := '0';
rx_lost_blocks_p1_o : out std_logic := '0';
......@@ -230,16 +262,21 @@ package streamers_pkg is
rx_lost_frames_cnt_o : out std_logic_vector(14 downto 0);
rx_latency_o : out std_logic_vector(27 downto 0);
rx_latency_valid_o : out std_logic;
rx_stat_overflow_p1_o : out std_logic;
rx_stat_match_p1_o : out std_logic;
rx_stat_late_p1_o : out std_logic;
rx_stat_timeout_p1_o : out std_logic;
rx_frame_p1_o : out std_logic;
rx_streamer_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default);
end component;
constant c_WRS_STATS_ARR_SIZE_OUT : integer := 18;
constant c_WRS_STATS_ARR_SIZE_OUT : integer := 24;
constant c_WRS_STATS_ARR_SIZE_IN : integer := 1;
component xrtx_streamers_stats is
generic (
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_clk_ref_rate : integer := 125000000;
g_cnt_width : integer := 50;
g_acc_width : integer := 64
);
......@@ -253,6 +290,9 @@ package streamers_pkg is
lost_frames_cnt_i : in std_logic_vector(14 downto 0);
rcvd_latency_i : in std_logic_vector(27 downto 0);
rcvd_latency_valid_i : in std_logic;
rx_stat_match_p1_i : in std_logic;
rx_stat_late_p1_i : in std_logic;
rx_stat_timeout_p1_i : in std_logic;
clk_ref_i : in std_logic;
tm_time_valid_i : in std_logic := '0';
tm_tai_i : in std_logic_vector(39 downto 0) := x"0000000000";
......@@ -266,6 +306,9 @@ package streamers_pkg is
lost_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
lost_block_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
latency_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_match_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_late_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_timeout_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
latency_acc_overflow_o : out std_logic;
latency_acc_o : out std_logic_vector(g_acc_width-1 downto 0);
latency_max_o : out std_logic_vector(27 downto 0);
......@@ -281,6 +324,7 @@ package streamers_pkg is
component xwr_streamers is
generic (
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_clk_ref_rate : integer := 125000000;
--tx/rx
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
......@@ -290,7 +334,8 @@ package streamers_pkg is
-- WB i/f
g_slave_mode : t_wishbone_interface_mode := CLASSIC;
g_slave_granularity : t_wishbone_address_granularity := BYTE;
g_simulation : integer := 0
g_simulation : integer := 0;
g_sim_cycle_counter_range : integer := 125000
);
port (
......@@ -329,4 +374,4 @@ package streamers_pkg is
);
end component;
end streamers_pkg;
\ No newline at end of file
end streamers_pkg;
......@@ -72,9 +72,15 @@ package streamers_priv_pkg is
tm_time_valid_i : in std_logic;
snapshot_ena_i : in std_logic := '0';
reset_stats_i : in std_logic;
rx_stat_match_p1_i : in std_logic;
rx_stat_late_p1_i : in std_logic;
rx_stat_timeout_p1_i : in std_logic;
rcvd_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
lost_frame_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
lost_block_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_match_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_late_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
rx_stat_timeout_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
latency_cnt_o : out std_logic_vector(g_cnt_width-1 downto 0);
latency_acc_overflow_o : out std_logic;
latency_acc_o : out std_logic_vector(g_acc_width-1 downto 0);
......@@ -82,26 +88,10 @@ package streamers_priv_pkg is
latency_min_o : out std_logic_vector(27 downto 0));
end component;
component wr_streamers_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_wr_streamers_in_registers;
regs_o : out t_wr_streamers_out_registers
);
end component;
-- component from wr-core/modules/timing
component pulse_stamper