wr_pps_gen: fixed ns_overflow assertion during counter adjustment bug

15662e50 · Tomasz Wlostowski · 03e145bf · 15662e50
Commit 15662e50 authored Apr 24, 2012 by Tomasz Wlostowski
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wr_pps_gen.vhd modules/wr_pps_gen/wr_pps_gen.vhd +2 -2

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--- a/modules/wr_pps_gen/wr_pps_gen.vhd
+++ b/modules/wr_pps_gen/wr_pps_gen.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-09-02
-- Last update: 2012-04-20
+-- Last update: 2012-04-23
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
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@@ -387,7 +387,7 @@ begin  -- behavioral

 -- got counter overflow:
        elsif(cntr_nsec = to_unsigned(c_PERIOD-2, cntr_nsec'length)) then
-          ns_overflow <= not adjust_in_progress_nsec;
+          ns_overflow <= '1';
          cntr_nsec   <= cntr_nsec + 1;
        elsif(cntr_nsec = to_unsigned(c_PERIOD-1, cntr_nsec'length)) then
          ns_overflow <= '0';