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White Rabbit core collection
Commit 11ab93ef authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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wrcore_v2: bugfixes

parent 4bd764dc
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Showing with 14 additions and 12 deletions
modules/wrc_core/wr_core.vhd
View file @ 11ab93ef
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk -- Author : Grzegorz Daniluk
-- Company : Elproma -- Company : Elproma
-- Created : 2011-02-02 -- Created : 2011-02-02
-- Last update: 2011-11-29 -- Last update: 2011-12-13
-- Platform : FPGA-generics -- Platform : FPGA-generics
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -66,7 +66,7 @@ entity wr_core is ...@@ -66,7 +66,7 @@ entity wr_core is
g_dpram_initf : string := ""; g_dpram_initf : string := "";
g_dpram_size : integer := 16384; --in 32-bit words g_dpram_size : integer := 16384; --in 32-bit words
g_interface_mode : t_wishbone_interface_mode := PIPELINED; g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE g_address_granularity : t_wishbone_address_granularity := WORD
); );
port( port(
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
...@@ -352,7 +352,7 @@ architecture struct of wr_core is ...@@ -352,7 +352,7 @@ architecture struct of wr_core is
class_core_i : in std_logic_vector(7 downto 0)); class_core_i : in std_logic_vector(7 downto 0));
end component; end component;
component chipscope_ila component chipscope_ila
port ( port (
CONTROL : inout std_logic_vector(35 downto 0); CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic; CLK : in std_logic;
...@@ -712,11 +712,11 @@ begin ...@@ -712,11 +712,11 @@ begin
generic map( generic map(
g_num_masters => 1, g_num_masters => 1,
g_num_slaves => 7, g_num_slaves => 7,
g_registered => false g_registered => true
) )
port map( port map(
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_n_i => rst_wrc_n, rst_n_i => rst_n_i,
-- Master connections (INTERCON is a slave) -- Master connections (INTERCON is a slave)
slave_i(0) => cbar_master_o(1), slave_i(0) => cbar_master_o(1),
slave_o(0) => cbar_master_i(1), slave_o(0) => cbar_master_i(1),
......
modules/wrc_core/wrc_periph.vhd
View file @ 11ab93ef
...@@ -226,9 +226,6 @@ begin ...@@ -226,9 +226,6 @@ begin
regs_o => sysc_regs_o regs_o => sysc_regs_o
); );
--slave_o(0).ack <= '0';
--slave_o(0).stall <= '0';
-------------------------------------- --------------------------------------
-- UART -- UART
-------------------------------------- --------------------------------------
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 11ab93ef
...@@ -499,6 +499,7 @@ architecture rtl of spec_top is ...@@ -499,6 +499,7 @@ architecture rtl of spec_top is
signal wrc_slave_i : t_wishbone_slave_in; signal wrc_slave_i : t_wishbone_slave_in;
signal wrc_slave_o : t_wishbone_slave_out; signal wrc_slave_o : t_wishbone_slave_out;
signal wb_adr : std_logic_vector(c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
begin begin
cmp_sys_clk_pll : PLL_BASE cmp_sys_clk_pll : PLL_BASE
...@@ -643,7 +644,7 @@ begin ...@@ -643,7 +644,7 @@ begin
g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB, g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB,
g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB, g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB,
g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH, g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH,
g_CSR_WB_MODE => "classic" g_CSR_WB_MODE => "pipelined"
) )
port map port map
( (
...@@ -700,7 +701,8 @@ begin ...@@ -700,7 +701,8 @@ begin
--------------------------------------------------------- ---------------------------------------------------------
-- Target Interface (Wishbone master) -- Target Interface (Wishbone master)
wb_clk_i => clk_sys, wb_clk_i => clk_sys,
wb_adr_o => wrc_slave_i.adr(c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0), --wb_adr_o => wrc_slave_i.adr(c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0),
wb_adr_o => wb_adr,
wb_dat_o => wrc_slave_i.dat, wb_dat_o => wrc_slave_i.dat,
wb_sel_o => wrc_slave_i.sel, wb_sel_o => wrc_slave_i.sel,
wb_stb_o => wrc_slave_i.stb, wb_stb_o => wrc_slave_i.stb,
...@@ -723,6 +725,9 @@ begin ...@@ -723,6 +725,9 @@ begin
dma_stall_i => dma_stall dma_stall_i => dma_stall
); );
wrc_slave_i.adr(16 downto 0) <= wb_adr(16 downto 0);
wrc_slave_i.adr(31 downto 17) <= (others=>'0');
process(clk_sys, rst) process(clk_sys, rst)
begin begin
if rising_edge(clk_sys) then if rising_edge(clk_sys) then
...@@ -746,8 +751,8 @@ begin ...@@ -746,8 +751,8 @@ begin
g_ep_rxbuf_size_log2 => 12, g_ep_rxbuf_size_log2 => 12,
g_dpram_initf => "", g_dpram_initf => "",
g_dpram_size => 16384, g_dpram_size => 16384,
g_interface_mode => CLASSIC, g_interface_mode => PIPELINED,
g_address_granularity => BYTE) g_address_granularity => WORD)
port map ( port map (
clk_sys_i => clk_sys, clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd, clk_dmtd_i => clk_dmtd,
......
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