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White Rabbit core collection
Commit 0f14c50b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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WR core: imported from master branch

parent 9d212620
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modules/wrc_core/wb_reset.vhd 0 → 100644
View file @ 0f14c50b
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core ZPU reset generator
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wb_reset.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-04
-- Last update: 2011-06-16
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WB_RESET is a reset signal generator for ZPU. It is controlled by wishbone
-- and is used by ZPU firmware loader(zpu-loader) to reset the processor during
-- copying the binary to dpram.
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-04-04 1.0 greg.d Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity wb_reset is
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
genrst_n_o : out std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end wb_reset;
architecture behaviour of wb_reset is
constant c_RST_REG : std_logic_vector(1 downto 0) := "00";
signal rst_reg : std_logic_vector(7 downto 0);
signal grst_n : std_logic_vector(20 downto 0);
signal ack_int : std_logic;
begin
process(clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
ack_int <= '0';
rst_reg <= (others => '0');
elsif(rising_edge(clk_i)) then
if(wb_stb_i = '1' and wb_cyc_i = '1' and ack_int = '0') then
if(wb_we_i = '1') then
case wb_addr_i is
when c_RST_REG =>
rst_reg <= wb_data_i(7 downto 0);
when others =>
end case;
end if;
ack_int <= '1';
else
ack_int <= '0';
end if;
end if;
end process;
wb_ack_o <= ack_int;
process(clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
grst_n <= (others => '1');
elsif(rising_edge(clk_i)) then
if(rst_reg(0) = '1') then
grst_n(0) <= '0';
else
grst_n(0) <= '1';
end if;
grst_n(grst_n'left downto 1) <= grst_n(grst_n'left-1 downto 0);
end if;
end process;
genrst_n_o <= grst_n(grst_n'left);
end behaviour;
modules/wrc_core/wr_core.vhd 0 → 100644
View file @ 0f14c50b
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wr_core.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-02
-- Last update: 2011-08-23
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WR PTP Core is a HDL module implementing a complete gigabit Ethernet
-- interface (MAC + PCS + PHY) with integrated PTP slave ordinary clock
-- compatible with White Rabbit protocol. It performs subnanosecond clock
-- synchronization via WR protocol and also acts as an Ethernet "gateway",
-- providing access to TX/RX interfaces of the built-in WR MAC.
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-02 1.0 greg.d Created
-------------------------------------------------------------------------------
-- TODO:
-- Testing
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wrcore_pkg.all;
use work.wbconmax_pkg.all;
use work.genram_pkg.all;
entity wr_core is
generic(
--if set to 1, then blocks in PCS use smaller calibration counter to speed
--up simulation
g_simulation : integer := 0;
g_virtual_uart : natural := 0;
g_ep_rxbuf_size_log2 : integer := 12;
g_dpram_initf : string := "";
g_dpram_size : integer := 16384; --in 32-bit words
g_num_gpio : integer := 8
);
port(
clk_sys_i : in std_logic;
-- DDMTD offset lcock (125.x MHz)
clk_dmtd_i : in std_logic;
-- Timing reference (125 MHz)
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
-----------------------------------------
--PPS gen
-----------------------------------------
pps_p_o : out std_logic;
-----------------------------------------
--Timing system
-----------------------------------------
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_dpll_load_p1_o : out std_logic;
dac_dpll_data_o : out std_logic_vector(15 downto 0);
-- PHY I/f
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(7 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(7 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(3 downto 0);
phy_rst_o : out std_logic;
phy_loopen_o : out std_logic;
-----------------------------------------
--GPIO
-----------------------------------------
gpio_o : out std_logic_vector(g_num_gpio-1 downto 0);
gpio_i : in std_logic_vector(g_num_gpio-1 downto 0);
gpio_dir_o : out std_logic_vector(g_num_gpio-1 downto 0);
-----------------------------------------
--UART
-----------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-----------------------------------------
--External WB interface
-----------------------------------------
wb_addr_i : in std_logic_vector(c_aw-1 downto 0);
wb_data_i : in std_logic_vector(c_dw-1 downto 0);
wb_data_o : out std_logic_vector(c_dw-1 downto 0);
wb_sel_i : in std_logic_vector(c_sw-1 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_ack_o : out std_logic;
--DEBUG
genrest_n : out std_logic;
dio_o : out std_logic_vector(3 downto 0)
);
end wr_core;
architecture struct of wr_core is
signal s_rst : std_logic;
signal s_rst_n : std_logic;
-----------------------------------------------------------------------------
--PPS generator
-----------------------------------------------------------------------------
signal s_pps_csync : std_logic;
signal ppsg_wb_i : t_wb_i;
signal ppsg_wb_o : t_wb_o;
-----------------------------------------------------------------------------
--Timing system
-----------------------------------------------------------------------------
signal hpll_wb_i : t_wb_i;
signal hpll_wb_o : t_wb_o;
signal dpll_wb_i : t_wb_i;
signal dpll_wb_o : t_wb_o;
-----------------------------------------------------------------------------
--Endpoint
-----------------------------------------------------------------------------
signal s_ep_rx_data_o : std_logic_vector(15 downto 0);
signal s_ep_rx_ctrl_o : std_logic_vector(4 - 1 downto 0);
signal s_ep_rx_bytesel_o : std_logic;
signal s_ep_rx_sof_p1_o : std_logic;
signal s_ep_rx_eof_p1_o : std_logic;
signal s_ep_rx_dreq_i : std_logic;
signal s_ep_rx_valid_o : std_logic;
signal s_ep_rx_rerror_p1_o : std_logic;
signal s_ep_tx_data_i : std_logic_vector(15 downto 0);
signal s_ep_tx_ctrl_i : std_logic_vector(4 - 1 downto 0);
signal s_ep_tx_bytesel_i : std_logic;
signal s_ep_tx_sof_p1_i : std_logic;
signal s_ep_tx_eof_p1_i : std_logic;
signal s_ep_tx_dreq_o : std_logic;
signal s_ep_tx_valid_i : std_logic;
signal s_ep_tx_terror_p1_o : std_logic;
signal txtsu_port_id_o : std_logic_vector(4 downto 0);
signal txtsu_frame_id_o : std_logic_vector(16 -1 downto 0);
signal txtsu_tsval_o : std_logic_vector(28 + 4 - 1 downto 0);
signal txtsu_valid_o : std_logic;
signal txtsu_ack_i : std_logic;
signal ep_wb_i : t_wb_i;
signal ep_wb_o : t_wb_o;
-----------------------------------------------------------------------------
--GTP
-----------------------------------------------------------------------------
signal s_gtp_tx_data_i : std_logic_vector(7 downto 0);
signal s_gtp_tx_k_i : std_logic;
signal s_gtp_tx_disparity_o : std_logic;
signal s_gtp_tx_enc_err_o : std_logic;
signal s_gtp_rx_data_o : std_logic_vector(7 downto 0);
signal s_gtp_rx_rbclk_o : std_logic;
signal s_gtp_rx_k_o : std_logic;
signal s_gtp_rx_enc_err_o : std_logic;
signal s_gtp_rx_bitslide_o : std_logic_vector(3 downto 0);
signal s_gtp_rst_i : std_logic;
signal s_gtp_loopen_i : std_logic;
constant c_mnic_memsize_log2 : integer := f_log2_size(g_dpram_size);
-----------------------------------------------------------------------------
--Mini-NIC
-----------------------------------------------------------------------------
signal s_mnic_mem_data_o : std_logic_vector(31 downto 0);
signal s_mnic_mem_addr_o : std_logic_vector(c_mnic_memsize_log2-1 downto 0);
signal s_mnic_mem_data_i : std_logic_vector(31 downto 0);
signal s_mnic_mem_wr_o : std_logic;
signal mnic_wb_i : t_wb_i;
signal mnic_wb_o : t_wb_o;
signal mnic_wb_irq_o : std_logic;
-----------------------------------------------------------------------------
--CPU
-----------------------------------------------------------------------------
signal zpu_wb_i : t_wb_o;
signal zpu_wb_o : t_wb_i;
signal lm32_iwb_i : t_wb_o;
signal lm32_iwb_o : t_wb_i;
signal lm32_jwb_i : t_wb_i;
signal lm32_jwb_o : t_wb_o;
signal lm32_dwb_i : t_wb_o;
signal lm32_dwb_o : t_wb_i;
-----------------------------------------------------------------------------
--Dual-port RAM
-----------------------------------------------------------------------------
signal dpram_wb_i : t_wb_i;
signal dpram_wb_o : t_wb_o;
-----------------------------------------------------------------------------
--WB GPIO
-----------------------------------------------------------------------------
--signal gpio_wb_i : t_wb_i;
--signal gpio_wb_o : t_wb_o;
-----------------------------------------------------------------------------
--WB UART
-----------------------------------------------------------------------------
--signal uart_wb_i : t_wb_i;
--signal uart_wb_o : t_wb_o;
--signal uart_rxd : std_logic;
--signal uart_txd : std_logic;
-----------------------------------------------------------------------------
--WB Peripherials
-----------------------------------------------------------------------------
signal periph_wb_i : t_wb_i;
signal periph_wb_o : t_wb_o;
-----------------------------------------------------------------------------
--WB intercon
-----------------------------------------------------------------------------
signal wbm_unused_i : t_wb_i;
signal wbs_unused_i : t_wb_o;
signal cnx_master_i : t_conmax_masters_i;
signal cnx_master_o : t_conmax_masters_o;
signal cnx_slave_i : t_conmax_slaves_i;
signal cnx_slave_o : t_conmax_slaves_o;
-----------------------------------------------------------------------------
--External WB interface
-----------------------------------------------------------------------------
signal ext_wb_i : t_wb_o;
signal ext_wb_o : t_wb_i;
--===========================--
-- For SPEC --
--===========================--
signal rst_wb_addr_o : std_logic_vector(17 downto 0);
signal rst_wb_data_i : std_logic_vector(31 downto 0);
signal rst_wb_data_o : std_logic_vector(31 downto 0);
signal rst_wb_sel_o : std_logic_vector(3 downto 0);
signal rst_wb_we_o : std_logic;
signal rst_wb_cyc_o : std_logic;
signal rst_wb_stb_o : std_logic;
signal rst_wb_ack_i : std_logic;
signal genrst_n : std_logic;
signal rst_wb_i : t_wb_i;
signal rst_wb_o : t_wb_o;
signal hpll_auxout : std_logic_vector(2 downto 0);
signal dmpll_auxout : std_logic_vector(2 downto 0);
signal clk_ref_slv : std_logic_vector(0 downto 0);
signal clk_rx_slv : std_logic_vector(0 downto 0);
signal s_dummy_addr : std_logic_vector(31 downto 0);
signal rst_n_inv : std_logic;
signal softpll_irq : std_logic;
signal lm32_irq_slv : std_logic_vector(0 downto 0);
signal trace_pc : std_logic_vector(31 downto 0);
signal trace_eret : std_logic;
signal trace_valid : std_logic;
begin
s_rst_n <= genrst_n and rst_n_i;
s_rst <= not s_rst_n;
-----------------------------------------------------------------------------
--PPS generator
-----------------------------------------------------------------------------
PPS_GEN : wrsw_pps_gen
port map(
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys_i,
rst_n_i => s_rst_n,
wb_addr_i => ppsg_wb_i.addr(3 downto 0),
wb_data_i => ppsg_wb_i.data,
wb_data_o => ppsg_wb_o.data,
wb_cyc_i => ppsg_wb_i.cyc,
wb_sel_i => ppsg_wb_i.sel,
wb_stb_i => ppsg_wb_i.stb,
wb_we_i => ppsg_wb_i.we,
wb_ack_o => ppsg_wb_o.ack,
-- Single-pulse PPS output for synchronizing endpoint to
pps_in_i => '0',
pps_csync_o => s_pps_csync,
pps_out_o => pps_p_o
);
U_SOFTPLL : wr_softpll
generic map (
g_deglitcher_threshold => 3000,
g_tag_bits => 20)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => s_rst_n,
clk_ref_i => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => phy_rx_rbclk_i,
dac_hpll_data_o => dac_hpll_data_o,
dac_hpll_load_o => dac_hpll_load_p1_o,
dac_dmpll_data_o => dac_dpll_data_o,
dac_dmpll_load_o => dac_dpll_load_p1_o,
wb_addr_i => dpll_wb_i.addr(3 downto 0),
wb_data_i => dpll_wb_i.data,
wb_data_o => dpll_wb_o.data,
wb_cyc_i => dpll_wb_i.cyc,
wb_sel_i => dpll_wb_i.sel,
wb_stb_i => dpll_wb_i.stb,
wb_we_i => dpll_wb_i.we,
wb_ack_o => dpll_wb_o.ack,
wb_irq_o => softpll_irq,
debug_o => dio_o);
-----------------------------------------------------------------------------
-- Endpoint
-----------------------------------------------------------------------------
WR_ENDPOINT : wrsw_endpoint
generic map(
g_simulation => g_simulation,
g_phy_mode => "GTP",
g_rx_buffer_size_log2 => g_ep_rxbuf_size_log2
)
port map(
-- Endpoint transmit reference clock. Must be 125 MHz +- 100 ppm
clk_ref_i => clk_ref_i,
-- reference clock / 2 (62.5 MHz, in-phase with refclk)
clk_sys_i => clk_sys_i,
-- DMTD sampling clock (125.x MHz) (from Timing system)
clk_dmtd_i => clk_dmtd_i,
-- sync reset (clk_sys_i domain), active LO
rst_n_i => rst_n_i,
-- PPS input (1 clk_ref_i cycle HI) for synchronizing timestamp counter
pps_csync_p1_i => s_pps_csync,
-------------------------------------------------------------------------
-- Ten-Bit PHY interface (TLK1221)
-------------------------------------------------------------------------
tbi_td_o => open,
tbi_enable_o => open,
tbi_syncen_o => open,
tbi_loopen_o => open,
tbi_prbsen_o => open,
tbi_rbclk_i => '0',
tbi_rd_i => "0000000000",
tbi_sync_pass_i => '0',
-------------------------------------------------------------------------
-- Xilinx GTP PHY Interace
-------------------------------------------------------------------------
gtp_tx_clk_i => phy_ref_clk_i,
gtp_tx_data_o => phy_tx_data_o,
gtp_tx_k_o => phy_tx_k_o,
gtp_tx_disparity_i => phy_tx_disparity_i,
gtp_tx_enc_err_i => phy_tx_enc_err_i,
gtp_rx_data_i => phy_rx_data_i,
gtp_rx_clk_i => phy_rx_rbclk_i,
gtp_rx_k_i => phy_rx_k_i,
gtp_rx_enc_err_i => phy_rx_enc_err_i,
gtp_rx_bitslide_i => phy_rx_bitslide_i,
gtp_rst_o => phy_rst_o,
gtp_loopen_o => phy_loopen_o,
-------------------------------------------------------------------------
-- WRF source (output of RXed packets)
-------------------------------------------------------------------------
rx_data_o => s_ep_rx_data_o,
rx_ctrl_o => s_ep_rx_ctrl_o,
rx_bytesel_o => s_ep_rx_bytesel_o,
rx_sof_p1_o => s_ep_rx_sof_p1_o,
rx_eof_p1_o => s_ep_rx_eof_p1_o,
rx_dreq_i => s_ep_rx_dreq_i,
rx_valid_o => s_ep_rx_valid_o,
rx_rabort_p1_i => '0',
rx_idle_o => open,
rx_rerror_p1_o => s_ep_rx_rerror_p1_o,
-------------------------------------------------------------------------
-- WRF Sink (input for the packets to be TXed)
-------------------------------------------------------------------------
tx_data_i => s_ep_tx_data_i,
tx_ctrl_i => s_ep_tx_ctrl_i,
tx_bytesel_i => s_ep_tx_bytesel_i,
tx_sof_p1_i => s_ep_tx_sof_p1_i,
tx_eof_p1_i => s_ep_tx_eof_p1_i,
tx_dreq_o => s_ep_tx_dreq_o,
tx_valid_i => s_ep_tx_valid_i,
tx_rerror_p1_i => '0',
tx_tabort_p1_i => '0',
tx_terror_p1_o => s_ep_tx_terror_p1_o,
-------------------------------------------------------------------------
-- TX timestamping unit interface
-------------------------------------------------------------------------
txtsu_port_id_o => txtsu_port_id_o,
txtsu_frame_id_o => txtsu_frame_id_o,
txtsu_tsval_o => txtsu_tsval_o,
txtsu_valid_o => txtsu_valid_o,
txtsu_ack_i => txtsu_ack_i,
-------------------------------------------------------------------------
-- RTU interface
-------------------------------------------------------------------------
rtu_full_i => '0',
rtu_almost_full_i => '0',
rtu_rq_strobe_p1_o => open,
rtu_rq_smac_o => open,
rtu_rq_dmac_o => open,
rtu_rq_vid_o => open,
rtu_rq_has_vid_o => open,
rtu_rq_prio_o => open,
rtu_rq_has_prio_o => open,
-------------------------------------------------------------------------
-- Wishbone bus
-------------------------------------------------------------------------
wb_cyc_i => ep_wb_i.cyc,
wb_stb_i => ep_wb_i.stb,
wb_we_i => ep_wb_i.we,
wb_sel_i => ep_wb_i.sel,
wb_addr_i => ep_wb_i.addr(5 downto 0),
wb_data_i => ep_wb_i.data,
wb_data_o => ep_wb_o.data,
wb_ack_o => ep_wb_o.ack
);
-----------------------------------------------------------------------------
-- Mini-NIC
-----------------------------------------------------------------------------
MINIC : wr_mini_nic
generic map(
g_memsize_log2 => c_mnic_memsize_log2,
g_buffer_little_endian => false
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => s_rst_n,
-------------------------------------------------------------------------
-- System memory i/f
-------------------------------------------------------------------------
mem_data_o => s_mnic_mem_data_o,
mem_addr_o => s_mnic_mem_addr_o,
mem_data_i => s_mnic_mem_data_i,
mem_wr_o => s_mnic_mem_wr_o,
-------------------------------------------------------------------------
-- WRF source/sink
-------------------------------------------------------------------------
--mNIC Source -> EP Sink
src_data_o => s_ep_tx_data_i,
src_ctrl_o => s_ep_tx_ctrl_i,
src_bytesel_o => s_ep_tx_bytesel_i,
src_sof_p1_o => s_ep_tx_sof_p1_i,
src_eof_p1_o => s_ep_tx_eof_p1_i,
src_dreq_i => s_ep_tx_dreq_o,
src_valid_o => s_ep_tx_valid_i,
src_error_p1_o => open,
src_error_p1_i => s_ep_tx_terror_p1_o,
--mNIC Sink <- EP Source
snk_data_i => s_ep_rx_data_o,
snk_ctrl_i => s_ep_rx_ctrl_o,
snk_bytesel_i => s_ep_rx_bytesel_o,
snk_sof_p1_i => s_ep_rx_sof_p1_o,
snk_eof_p1_i => s_ep_rx_eof_p1_o,
snk_dreq_o => s_ep_rx_dreq_i,
snk_valid_i => s_ep_rx_valid_o,
snk_error_p1_o => open,
snk_error_p1_i => s_ep_rx_rerror_p1_o,
-------------------------------------------------------------------------
-- TXTSU i/f
-------------------------------------------------------------------------
txtsu_port_id_i => txtsu_port_id_o,
txtsu_frame_id_i => txtsu_frame_id_o,
txtsu_tsval_i => txtsu_tsval_o,
txtsu_valid_i => txtsu_valid_o,
txtsu_ack_o => txtsu_ack_i,
-------------------------------------------------------------------------
-- Wishbone slave
-------------------------------------------------------------------------
wb_cyc_i => mnic_wb_i.cyc,
wb_stb_i => mnic_wb_i.stb,
wb_we_i => mnic_wb_i.we,
wb_sel_i => mnic_wb_i.sel,
wb_addr_i => mnic_wb_i.addr(3 downto 0),
wb_data_i => mnic_wb_i.data,
wb_data_o => mnic_wb_o.data,
wb_ack_o => mnic_wb_o.ack,
wb_irq_o => open
);
mnic_wb_irq_o <= '0';
lm32_irq_slv(0) <= softpll_irq; -- according to the doc, it's active low.
LM32_CORE : wrc_lm32
generic map (
g_addr_width => c_aw,
g_num_irqs => 1)
port map (
clk_i => clk_sys_i,
rst_n_i => s_rst_n,
irq_i => lm32_irq_slv,
iwb_adr_o => lm32_iwb_o.addr,
iwb_dat_o => lm32_iwb_o.data,
iwb_dat_i => lm32_iwb_i.data,
iwb_cyc_o => lm32_iwb_o.cyc,
iwb_stb_o => lm32_iwb_o.stb,
iwb_sel_o => lm32_iwb_o.sel,
iwb_we_o => lm32_iwb_o.we,
iwb_ack_i => lm32_iwb_i.ack,
dwb_adr_o => lm32_dwb_o.addr,
dwb_dat_o => lm32_dwb_o.data,
dwb_dat_i => lm32_dwb_i.data,
dwb_cyc_o => lm32_dwb_o.cyc,
dwb_stb_o => lm32_dwb_o.stb,
dwb_sel_o => lm32_dwb_o.sel,
dwb_we_o => lm32_dwb_o.we,
dwb_ack_i => lm32_dwb_i.ack,
jwb_adr_i => lm32_jwb_i.addr,
jwb_dat_i => lm32_jwb_i.data,
jwb_dat_o => lm32_jwb_o.data,
jwb_cyc_i => lm32_jwb_i.cyc,
jwb_stb_i => lm32_jwb_i.stb,
jwb_sel_i => lm32_jwb_i.sel,
jwb_we_i => lm32_jwb_i.we,
jwb_ack_o => lm32_jwb_o.ack,
trace_pc_o => trace_pc,
trace_pc_valid_o => trace_valid,
trace_eret_o => trace_eret);
-----------------------------------------------------------------------------
-- Dual-port RAM
-----------------------------------------------------------------------------
DPRAM : wrc_dpram
generic map(
g_size => g_dpram_size,
g_init_file => g_dpram_initf
)
port map(
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
--PORT A (Wishbone)
wb_addr_i => dpram_wb_i.addr(13 downto 0),
wb_data_i => dpram_wb_i.data,
wb_data_o => dpram_wb_o.data,
wb_sel_i => dpram_wb_i.sel,
wb_cyc_i => dpram_wb_i.cyc,
wb_stb_i => dpram_wb_i.stb,
wb_we_i => dpram_wb_i.we,
wb_ack_o => dpram_wb_o.ack,
--PORT B (miniNIC)
mem_addr_i => s_mnic_mem_addr_o,
mem_data_i => s_mnic_mem_data_o,
mem_data_o => s_mnic_mem_data_i,
mem_wr_i => s_mnic_mem_wr_o
);
-----------------------------------------------------------------------------
-- WB Peripherials
-----------------------------------------------------------------------------
PERIPH : wrc_periph
generic map(
g_gpio_pins => g_num_gpio,
g_virtual_uart => g_virtual_uart,
g_tics_period => 62500
)
port map(
clk_sys_i => clk_sys_i,
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_i,
gpio_o => gpio_o,
gpio_i => gpio_i,
gpio_dir_o => gpio_dir_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
genrst_n_o => genrst_n,
wb_addr_i => periph_wb_i.addr(11 downto 0),
wb_data_i => periph_wb_i.data,
wb_data_o => periph_wb_o.data,
wb_sel_i => periph_wb_i.sel,
wb_stb_i => periph_wb_i.stb,
wb_cyc_i => periph_wb_i.cyc,
wb_we_i => periph_wb_i.we,
wb_ack_o => periph_wb_o.ack
);
-- gpio_o <= gpio_b;
-----------------------------------------------------------------------------
-- External WB interface
-----------------------------------------------------------------------------
ext_wb_o.addr <= wb_addr_i;
ext_wb_o.data <= wb_data_i;
ext_wb_o.sel <= wb_sel_i;
ext_wb_o.we <= wb_we_i;
ext_wb_o.cyc <= wb_cyc_i;
ext_wb_o.stb <= wb_stb_i;
wb_data_o <= ext_wb_i.data;
wb_ack_o <= ext_wb_i.ack;
-----------------------------------------------------------------------------
-- WB intercon
-----------------------------------------------------------------------------
wbm_unused_i.data <= (others => '0');
wbm_unused_i.addr <= (others => '0');
wbm_unused_i.sel <= (others => '0');
wbm_unused_i.we <= '0';
wbm_unused_i.cyc <= '0';
wbm_unused_i.stb <= '0';
wbs_unused_i.data <= (others => '0');
wbs_unused_i.ack <= '0';
wbs_unused_i.err <= '0';
wbs_unused_i.rty <= '0';
rst_n_inv <= not rst_n_i;
WB_CON : wb_conmax_top
generic map(
g_rf_addr => 15
)
port map(
clk_i => clk_sys_i,
rst_i => rst_n_inv,
wb_masters_i => cnx_master_i,
wb_masters_o => cnx_master_o,
wb_slaves_i => cnx_slave_i,
wb_slaves_o => cnx_slave_o
);
cnx_master_i(0) <= lm32_iwb_o;
cnx_master_i(2) <= lm32_dwb_o;
lm32_iwb_i <= cnx_master_o(0);
lm32_dwb_i <= cnx_master_o(2);
cnx_master_i(1) <= ext_wb_o;
cnx_master_i(3) <= wbm_unused_i;
cnx_master_i(4) <= wbm_unused_i;
cnx_master_i(5) <= wbm_unused_i;
cnx_master_i(6) <= wbm_unused_i;
cnx_master_i(7) <= wbm_unused_i;
ext_wb_i <= cnx_master_o(1);
cnx_slave_i(0) <= dpram_wb_o;
cnx_slave_i(1) <= mnic_wb_o;
cnx_slave_i(2) <= ep_wb_o;
cnx_slave_i(3) <= hpll_wb_o;
cnx_slave_i(4) <= dpll_wb_o;
cnx_slave_i(5) <= ppsg_wb_o;
cnx_slave_i(6) <= periph_wb_o; --gpio_wb_o;
cnx_slave_i(7) <= lm32_jwb_o;
cnx_slave_i(8) <= wbs_unused_i;
cnx_slave_i(9) <= wbs_unused_i;
cnx_slave_i(10) <= wbs_unused_i;
cnx_slave_i(11) <= wbs_unused_i;
cnx_slave_i(12) <= wbs_unused_i;
cnx_slave_i(13) <= wbs_unused_i;
cnx_slave_i(14) <= wbs_unused_i;
cnx_slave_i(15) <= wbs_unused_i;
dpram_wb_i <= cnx_slave_o(0);
mnic_wb_i <= cnx_slave_o(1);
ep_wb_i <= cnx_slave_o(2);
hpll_wb_i <= cnx_slave_o(3);
dpll_wb_i <= cnx_slave_o(4);
ppsg_wb_i <= cnx_slave_o(5);
periph_wb_i <= cnx_slave_o(6);
lm32_jwb_i <= cnx_slave_o(7);
end struct;
modules/wrc_core/wrc_dpram.vhd 0 → 100644
View file @ 0f14c50b
-------------------------------------------------------------------------------
-- Title : Dual-port RAM for WR core
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrc_dpram.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-15
-- Last update: 2011-07-18
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Dual port RAM from genrams with wishbone interface
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-15 1.0 greg.d Created
-- 2011-06-09 1.01 twlostow Removed unnecessary generics
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
entity wrc_dpram is
generic(
g_size : natural := 16384; -- 16 * 32bit = 64kB
g_init_file : string := ""
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
--PORT A (Wishbone)
wb_addr_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
--PORT B (miniNIC)
mem_addr_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_data_o : out std_logic_vector(31 downto 0);
mem_wr_i : in std_logic
);
end wrc_dpram;
architecture struct of wrc_dpram is
signal s_wb_ack_o : std_logic;
signal muxed_we : std_logic;
signal s_bwea : std_logic_vector(3 downto 0);
signal s_bweb : std_logic_vector(3 downto 0);
begin
wb_ack_o <= s_wb_ack_o;
DPRAM : generic_dpram
generic map(
-- standard parameters
g_data_width => 32,
g_size => g_size,
g_with_byte_enable => true,
g_addr_conflict_resolution => "read_first",
g_init_file => g_init_file,
g_dual_clock => false
)
port map(
rst_n_i => rst_n_i,
-- Port A
clka_i => clk_i,
bwea_i => s_bwea,
wea_i => muxed_we, --wb_we_i,
aa_i => wb_addr_i,
da_i => wb_data_i,
qa_o => wb_data_o,
-- Port B
clkb_i => clk_i,
bweb_i => s_bweb,
web_i => mem_wr_i,
ab_i => mem_addr_i,
db_i => mem_data_i,
qb_o => mem_data_o
);
s_bwea <= wb_sel_i when (wb_we_i = '1' and wb_stb_i = '1' and wb_cyc_i = '1') else "0000";
s_bweb <= (others => mem_wr_i);
muxed_we <= wb_we_i when (wb_stb_i='1' and wb_cyc_i='1') else '0';
process(clk_i)
begin
if(rising_edge(clk_i)) then
if(rst_n_i = '0') then
s_wb_ack_o <= '0';
else
if(s_wb_ack_o = '1') then
s_wb_ack_o <= '0';
else
s_wb_ack_o <= wb_cyc_i and wb_stb_i;
end if;
end if;
end if;
end process;
end struct;
modules/wrc_core/wrc_periph.vhd 0 → 100644
View file @ 0f14c50b
-------------------------------------------------------------------------------
-- Title : WhiteRabbit PTP Core peripherials
-- Project : WhiteRabbit
-------------------------------------------------------------------------------
-- File : wrc_periph.vhd
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-04
-- Last update: 2011-07-18
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- WRC_PERIPH is a single WB slave which includes all 'small' WB peripherials
-- needed for WR PTP Core. It has: wb_gpio_port, wb_simple_uart, wb_tics and
-- wb_reset.
-- All those modules share Wishbone Slave interface, and the address bus is
-- used to choose one of them at a time.
--
-- wb_addr_i(11:0):
-- (11) -> select wb_reset
-- (10) -> select wb_tics
-- (9) -> select wb_uart
-- (8) -> select wb_gpio
-- (7:0)-> address shared between wb modules inside wrc_periph
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-04-04 1.0 greg.d Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wrcore_pkg.all;
entity wrc_periph is
generic(
g_gpio_pins : natural := 8;
g_virtual_uart : natural := 0;
g_tics_period: integer
);
port(
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
gpio_o : out std_logic_vector(g_gpio_pins-1 downto 0);
gpio_i : in std_logic_vector(g_gpio_pins-1 downto 0);
gpio_dir_o : out std_logic_vector(g_gpio_pins-1 downto 0);
uart_rxd_i: in std_logic;
uart_txd_o: out std_logic;
genrst_n_o: out std_logic;
wb_addr_i : in std_logic_vector(11 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end wrc_periph;
architecture struct of wrc_periph is
component wb_tics
generic (
g_period : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
component wb_reset
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
genrst_n_o : out std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
component wb_simple_uart
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic);
end component;
component wb_virtual_uart
port(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end component;
component wb_gpio_port
generic (
g_num_pins : natural;
g_with_builtin_tristates : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_sel_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
type t_wbdata is array(3 downto 0) of std_logic_vector(31 downto 0);
signal wb_cycs_i : std_logic_vector(3 downto 0);
signal wb_stbs_i : std_logic_vector(3 downto 0);
signal wb_acks_o : std_logic_vector(3 downto 0);
signal wb_dats_o : t_wbdata;
signal wb_ack_int : std_logic;
begin
--TRIG3(11 downto 0) <= wb_addr_i(11 downto 0);
-- TRIG3(21 downto 12) <= (others => '0');
-- TRIG3(31 downto 28) <= wb_sel_i;
-- TRIG3(22) <= wb_cyc_i;
-- TRIG3(23) <= wb_stb_i;
-- TRIG3(24) <= wb_we_i;
-- TRIG3(25) <= wb_ack_int;
-- TRIG0 <= wb_data_i;
-- TRIG2(3 downto 0) <= wb_cycs_i;
-- TRIG2(7 downto 4) <= wb_acks_o;
wb_ack_o <= wb_ack_int;
GENWB:
for I in 0 to 3 generate
wb_cycs_i(I) <= wb_cyc_i and wb_addr_i(8+I);
wb_stbs_i(I) <= wb_stb_i and wb_addr_i(8+I);
end generate;
wb_ack_int <= wb_acks_o(0) when (wb_addr_i(11 downto 8)="0001") else
wb_acks_o(1) when (wb_addr_i(11 downto 8)="0010") else
wb_acks_o(2) when (wb_addr_i(11 downto 8)="0100") else
wb_acks_o(3) when (wb_addr_i(11 downto 8)="1000") else
'0';
wb_data_o <= wb_dats_o(0) when (wb_addr_i(11 downto 8)="0001") else
wb_dats_o(1) when (wb_addr_i(11 downto 8)="0010") else
wb_dats_o(2) when (wb_addr_i(11 downto 8)="0100") else
wb_dats_o(3) when (wb_addr_i(11 downto 8)="1000") else
(others=>'0');
GPIO: wb_gpio_port
generic map(
g_num_pins => g_gpio_pins,
g_with_builtin_tristates => false)
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_sel_i => wb_sel_i(0),
wb_cyc_i => wb_cycs_i(0),
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_adr_i => wb_addr_i(5 downto 0),
wb_dat_i => wb_data_i,
wb_dat_o => wb_dats_o(0),
wb_ack_o => wb_acks_o(0),
gpio_out_o => gpio_o,
gpio_in_i => gpio_i,
gpio_oen_o => gpio_dir_o
);
GEN_UART: if(g_virtual_uart = 0) generate
UART: wb_simple_uart
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_addr_i => wb_addr_i(1 downto 0),
wb_data_i => wb_data_i,
wb_data_o => wb_dats_o(1),
wb_cyc_i => wb_cycs_i(1),
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_acks_o(1),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o
);
end generate;
GEN_VIRTUART: if(g_virtual_uart = 1) generate
VIRTUAL_UART: wb_virtual_uart
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_addr_i => wb_addr_i(2 downto 0),
wb_data_i => wb_data_i,
wb_data_o => wb_dats_o(1),
wb_cyc_i => wb_cycs_i(1),
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_acks_o(1)
);
end generate;
TICS: wb_tics
generic map (
g_period => g_tics_period)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_addr_i => wb_addr_i(1 downto 0),
wb_data_i => wb_data_i,
wb_data_o => wb_dats_o(2),
wb_cyc_i => wb_cycs_i(2),
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_acks_o(2)
);
RST_GEN: wb_reset
port map(
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
genrst_n_o => genrst_n_o,
wb_addr_i => wb_addr_i(1 downto 0),
wb_data_i => wb_data_i,
wb_data_o => wb_dats_o(3),
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stbs_i(3),
wb_cyc_i => wb_cycs_i(3),
wb_we_i => wb_we_i,
wb_ack_o => wb_acks_o(3)
);
end struct;
modules/wrc_core/wrcore_pkg.vhd 0 → 100644
View file @ 0f14c50b
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
use work.wbconmax_pkg.all;
package wrcore_pkg is
component wb_conmax_top
generic (
g_rf_addr : integer range 0 to 15);
port (
clk_i : std_logic;
rst_i : std_logic;
wb_masters_i : in t_conmax_masters_i;
wb_masters_o : out t_conmax_masters_o;
wb_slaves_i : in t_conmax_slaves_i;
wb_slaves_o : out t_conmax_slaves_o);
end component;
-----------------------------------------------------------------------------
--PPS generator
-----------------------------------------------------------------------------
component wrsw_pps_gen
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
pps_in_i : in std_logic;
pps_csync_o : out std_logic;
pps_out_o : out std_logic);
end component;
-----------------------------------------------------------------------------
--WR Endpoint
-----------------------------------------------------------------------------
component wrsw_endpoint is
generic (
g_simulation : integer;
g_phy_mode : string := "TBI";
g_rx_buffer_size_log2 : integer := 12);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
rst_n_i : in std_logic;
pps_csync_p1_i : in std_logic;
--TBI
tbi_td_o : out std_logic_vector(9 downto 0);
tbi_enable_o : out std_logic;
tbi_syncen_o : out std_logic;
tbi_loopen_o : out std_logic;
tbi_prbsen_o : out std_logic;
tbi_rbclk_i : in std_logic;
tbi_rd_i : in std_logic_vector(9 downto 0);
tbi_sync_pass_i : in std_logic;
--GTP
gtp_tx_clk_i : in std_logic;
gtp_tx_data_o : out std_logic_vector(7 downto 0);
gtp_tx_k_o : out std_logic;
gtp_tx_disparity_i : in std_logic;
gtp_tx_enc_err_i : in std_logic;
gtp_rx_data_i : in std_logic_vector(7 downto 0);
gtp_rx_clk_i : in std_logic;
gtp_rx_k_i : in std_logic;
gtp_rx_enc_err_i : in std_logic;
gtp_rx_bitslide_i : in std_logic_vector(3 downto 0);
gtp_rst_o : out std_logic;
gtp_loopen_o : out std_logic;
--WRF Source
rx_data_o : out std_logic_vector(15 downto 0);
rx_ctrl_o : out std_logic_vector(4 - 1 downto 0);
rx_bytesel_o : out std_logic;
rx_sof_p1_o : out std_logic;
rx_eof_p1_o : out std_logic;
rx_dreq_i : in std_logic;
rx_valid_o : out std_logic;
rx_rabort_p1_i : in std_logic;
rx_idle_o : out std_logic;
rx_rerror_p1_o : out std_logic;
--WRF Sink
tx_data_i : in std_logic_vector(15 downto 0);
tx_ctrl_i : in std_logic_vector(4 -1 downto 0);
tx_bytesel_i : in std_logic;
tx_sof_p1_i : in std_logic;
tx_eof_p1_i : in std_logic;
tx_dreq_o : out std_logic;
tx_valid_i : in std_logic;
tx_rerror_p1_i : in std_logic;
tx_tabort_p1_i : in std_logic;
tx_terror_p1_o : out std_logic;
--TXTSU
txtsu_port_id_o : out std_logic_vector(4 downto 0);
txtsu_frame_id_o : out std_logic_vector(16 -1 downto 0);
txtsu_tsval_o : out std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_o : out std_logic;
txtsu_ack_i : in std_logic;
--RTU
rtu_full_i : in std_logic;
rtu_almost_full_i : in std_logic;
rtu_rq_strobe_p1_o : out std_logic;
rtu_rq_smac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_dmac_o : out std_logic_vector(48 - 1 downto 0);
rtu_rq_vid_o : out std_logic_vector(12 - 1 downto 0);
rtu_rq_has_vid_o : out std_logic;
rtu_rq_prio_o : out std_logic_vector(3-1 downto 0);
rtu_rq_has_prio_o : out std_logic;
--WB
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic
);
end component;
-----------------------------------------------------------------------------
--Mini NIC
-----------------------------------------------------------------------------
component wr_mini_nic is
generic (
g_memsize_log2 : integer := 14;
g_buffer_little_endian : boolean := true
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- System memory i/f
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
-- WRF source/sink
src_data_o : out std_logic_vector(15 downto 0);
src_ctrl_o : out std_logic_vector(4 - 1 downto 0);
src_bytesel_o : out std_logic;
src_sof_p1_o : out std_logic;
src_eof_p1_o : out std_logic;
src_dreq_i : in std_logic;
src_valid_o : out std_logic;
src_error_p1_o : out std_logic;
src_error_p1_i : in std_logic;
snk_data_i : in std_logic_vector(15 downto 0);
snk_ctrl_i : in std_logic_vector(4 -1 downto 0);
snk_bytesel_i : in std_logic;
snk_sof_p1_i : in std_logic;
snk_eof_p1_i : in std_logic;
snk_dreq_o : out std_logic;
snk_valid_i : in std_logic;
snk_error_p1_o : out std_logic;
snk_error_p1_i : in std_logic;
-- TXTSU i/f
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 -1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_valid_i : in std_logic;
txtsu_ack_o : out std_logic;
--WB
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
wb_irq_o : out std_logic
);
end component;
-----------------------------------------------------------------------------
--Dual-port RAM
-----------------------------------------------------------------------------
component wrc_dpram is
generic(
g_size : natural := 16; -- 16 * 32bit = 64kB
g_init_file : string := ""
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
--PORT A (Wishbone)
wb_addr_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
--PORT B (miniNIC)
mem_addr_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_data_o : out std_logic_vector(31 downto 0);
mem_wr_i : in std_logic
);
end component;
component wrc_periph
generic (
g_gpio_pins : natural;
g_virtual_uart : natural;
g_tics_period : integer);
port (
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
gpio_o : out std_logic_vector(g_gpio_pins-1 downto 0);
gpio_i : in std_logic_vector(g_gpio_pins-1 downto 0);
gpio_dir_o : out std_logic_vector(g_gpio_pins-1 downto 0);
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
genrst_n_o : out std_logic;
wb_addr_i : in std_logic_vector(11 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
component wb_reset
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
genrst_n_o : out std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic);
end component;
component wrc_lm32
generic (
g_addr_width : integer;
g_num_irqs : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(g_num_irqs-1 downto 0);
iwb_adr_o : out std_logic_vector(g_addr_width-1 downto 0);
iwb_dat_o : out std_logic_vector(31 downto 0);
iwb_dat_i : in std_logic_vector(31 downto 0);
iwb_cyc_o : out std_logic;
iwb_stb_o : out std_logic;
iwb_sel_o : out std_logic_vector(3 downto 0);
iwb_we_o : out std_logic;
iwb_ack_i : in std_logic;
dwb_adr_o : out std_logic_vector(g_addr_width-1 downto 0);
dwb_dat_o : out std_logic_vector(31 downto 0);
dwb_dat_i : in std_logic_vector(31 downto 0);
dwb_cyc_o : out std_logic;
dwb_stb_o : out std_logic;
dwb_sel_o : out std_logic_vector(3 downto 0);
dwb_we_o : out std_logic;
dwb_ack_i : in std_logic;
jwb_adr_i : in std_logic_vector(g_addr_width-1 downto 0);
jwb_dat_i : in std_logic_vector(31 downto 0);
jwb_dat_o : out std_logic_vector(31 downto 0);
jwb_cyc_i : in std_logic;
jwb_stb_i : in std_logic;
jwb_sel_i : in std_logic_vector(3 downto 0);
jwb_we_i : in std_logic;
jwb_ack_o : out std_logic;
trace_pc_o : out std_logic_vector(31 downto 0);
trace_pc_valid_o : out std_logic;
trace_eret_o : out std_logic);
end component;
component wr_softpll
generic (
g_deglitcher_threshold : integer;
g_tag_bits : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
dac_hpll_load_o : out std_logic;
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
debug_o: out std_logic_vector(3 downto 0));
end component;
end wrcore_pkg;
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