repaired pll_clk_sel_o being inverted

0c446e81 · Peter Jansweijer · 84677b24 · 0c446e81
Commit 0c446e81 authored Sep 21, 2020 by Peter Jansweijer
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wrc_periph.vhd modules/wrc_core/wrc_periph.vhd +2 -2

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--- a/modules/wrc_core/wrc_periph.vhd
+++ b/modules/wrc_core/wrc_periph.vhd
@@ -566,9 +566,9 @@ begin
       end if;
       if(sysc_regs_o.gpsr_pll_clk_sel_o = '1') then
-         pll_clk_sel_o <= '0';
-       elsif(sysc_regs_o.gpcr_pll_clk_sel_o = '1') then
         pll_clk_sel_o <= '1';
+       elsif(sysc_regs_o.gpcr_pll_clk_sel_o = '1') then
+         pll_clk_sel_o <= '0';
       end if;
       if(sysc_regs_o.gpsr_pll_wr_mode0_o = '1') then