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White Rabbit core collection
Commit 0a9be523 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_endpoint: endpoint_private_pkg.vhd: removed obsolete functions

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modules/wr_endpoint/endpoint_private_pkg.vhd
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......@@ -382,146 +382,6 @@ package body endpoint_private_pkg is
-- FIFO "packer" function. Packs frame data and status signals into a single
-- 18-bit word, matching the optimum data width of most FPGA RAMs/FIFOs. (2x
-- 8+1 bits)
--function f_pack_fifo_contents (
-- data : std_logic_vector;
-- sof : std_logic;
-- eof : std_logic;
-- bytesel : std_logic;
-- error : std_logic;
-- has_rx_timestamp : std_logic := '0';
-- early_eof : boolean := false) return std_logic_vector is
-- variable dout : std_logic_vector(17 downto 0);
--begin
-- -- the encodings are slightly different:
-- -- - if early_eof == 1, the target needs the EOF information along with the last data word.
-- -- This is the case for ep_tx_pcs.
-- -- - if early_eof == 0, EOF is an independent transfer
-- if(early_eof) then
-- if(sof = '1' or error = '1') then
-- -- tag = 01
-- dout(17 downto 16) := "01";
-- dout(15) := sof;
-- dout(14) := 'X';
-- dout(13) := error;
-- dout(12 downto 0) := (others => 'X');
-- elsif(eof = '1') then
-- -- tag = 1x
-- dout(17) := '1';
-- dout(16) := bytesel;
-- dout(15 downto 0) := data;
-- else
-- -- tag = 00
-- dout(17) := '0';
-- dout(16) := '0';
-- dout(15 downto 0) := data;
-- end if;
-- else
-- if(sof = '1' or error = '1' or eof = '1') then
-- -- tag = 01
-- dout(16) := '1';
-- dout(15) := sof;
-- dout(14) := eof;
-- dout(13) := error;
-- dout(12) := has_rx_timestamp;
-- dout(11 downto 0) := (others => 'X');
-- else
-- dout(17) := bytesel;
-- dout(16) := '0';
-- dout(15 downto 0) := data;
-- end if;
-- end if;
-- return dout;
--end f_pack_fifo_contents;
--function f_fifo_is_data(data : in std_logic_vector;
-- valid : in std_logic;
-- early_eof : boolean := false)
-- return std_logic is
--begin
-- if(early_eof) then
-- return not (not data(17) and data(16)) and valid;
-- else
-- return not data(16) and valid;
-- end if;
--end f_fifo_is_data;
--function f_fifo_is_sof
-- (data : in std_logic_vector;
-- valid : in std_logic;
-- early_eof : boolean := false) return std_logic is
--begin
-- if (early_eof and valid = '1' and data(17) = '0' and data(16) = '1' and data(15) = '1') then
-- return '1';
-- elsif(not early_eof and valid = '1' and data(16) = '1' and data(15) = '1') then
-- return '1';
-- else
-- return '0';
-- end if;
--end f_fifo_is_sof;
--function f_fifo_is_eof
-- (data : in std_logic_vector;
-- valid : in std_logic;
-- early_eof : boolean := false) return std_logic is
--begin
-- if (early_eof and valid = '1' and data(17) = '1') then
-- return '1';
-- elsif(not early_eof and valid = '1' and data(16) = '1' and data(14) = '1') then
-- return '1';
-- else
-- return '0';
-- end if;
--end f_fifo_is_eof;
--function f_fifo_is_error
-- (data : in std_logic_vector;
-- valid : in std_logic;
-- early_eof : boolean := false) return std_logic is
--begin
-- if (early_eof and valid = '1' and data(17) = '0' and data(16) = '1' and data(13) = '1') then
-- return '1';
-- elsif(not early_eof and valid = '1' and data(16) = '1' and data(13) = '1') then
-- return '1';
-- else
-- return '0';
-- end if;
--end f_fifo_is_error;
--function f_fifo_has_rx_timestamp
-- (data : in std_logic_vector;
-- valid : in std_logic;
-- early_eof : boolean := false) return std_logic is
--begin
-- if(not early_eof and valid = '1' and data(16) = '1' and data(13) = '1') then
-- return data(12);
-- else
-- return 0;
-- end if;
--end f_fifo_has_rx_timestamp;
--function f_fifo_is_single_byte
-- (data : in std_logic_vector;
-- valid : in std_logic;
-- early_eof : boolean := false) return std_logic is
--begin
-- if (early_eof and valid = '1' and data(17) = '1') then
-- return data(16);
-- elsif(not early_eof and valid = '1' and data(16) = '0') then
-- return data(17);
-- else
-- return '0';
-- end if;
--end f_fifo_is_single_byte;
end endpoint_private_pkg;
......
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