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White Rabbit core collection
Commit 077b3e01 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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cute_wr: xil_multiboot performs clock division, it can run with 62.5MHz

parent 13169b65
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Showing with 3 additions and 16 deletions
board/cute/xwrc_board_cute.vhd
View file @ 077b3e01
...@@ -371,8 +371,6 @@ architecture struct of xwrc_board_cute is ...@@ -371,8 +371,6 @@ architecture struct of xwrc_board_cute is
signal aux_master_out : t_wishbone_master_out; signal aux_master_out : t_wishbone_master_out;
signal aux_master_in : t_wishbone_master_in := cc_dummy_master_in; signal aux_master_in : t_wishbone_master_in := cc_dummy_master_in;
signal multiboot_wb_out : t_wishbone_master_out;
signal multiboot_wb_in : t_wishbone_master_in;
signal multiboot_slave_out : t_wishbone_slave_out; signal multiboot_slave_out : t_wishbone_slave_out;
signal multiboot_slave_in : t_wishbone_slave_in := cc_dummy_slave_in; signal multiboot_slave_in : t_wishbone_slave_in := cc_dummy_slave_in;
...@@ -678,23 +676,12 @@ U_WRPC_MULTIBOOT: if (g_multiboot_enable = true) generate ...@@ -678,23 +676,12 @@ U_WRPC_MULTIBOOT: if (g_multiboot_enable = true) generate
aux_master_in <= multiboot_slave_out; aux_master_in <= multiboot_slave_out;
aux_master_o <= cc_dummy_master_out; aux_master_o <= cc_dummy_master_out;
cmp_clock_crossing: xwb_clock_crossing
port map (
slave_clk_i => clk_pll_62m5,
slave_rst_n_i => rst_62m5_n,
slave_i => multiboot_slave_in,
slave_o => multiboot_slave_out,
master_clk_i => clk_20m_vcxo_i,
master_rst_n_i => rst_62m5_n,
master_i => multiboot_wb_in,
master_o => multiboot_wb_out);
u_multiboot: xwb_xil_multiboot u_multiboot: xwb_xil_multiboot
port map ( port map (
clk_i => clk_20m_vcxo_i, clk_i => clk_pll_62m5,
rst_n_i => rst_62m5_n, rst_n_i => rst_62m5_n,
wbs_i => multiboot_wb_out, wbs_i => multiboot_slave_in,
wbs_o => multiboot_wb_in, wbs_o => multiboot_slave_out,
spi_cs_n_o => open, spi_cs_n_o => open,
spi_sclk_o => open, spi_sclk_o => open,
spi_mosi_o => open, spi_mosi_o => open,
......
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