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White Rabbit core collection
Commit 065cc1de authored by Qiang Du's avatar Qiang Du
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enabled data2bmm to replace wrc.elf in bit file using top/cute_wr/wr_core_demo/cute.bmm 

See http://www.ohwr.org/issues/1006
parent dbaf0221
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Showing with 172 additions and 8 deletions
syn/cute_wr/wr_core_demo/cute_top.cmd_bmm 0 → 100755
View file @ 065cc1de
#xst -intstyle ise -ifn "/home/du/work/wr/wr-cores/syn/cute_wr/wr_core_demo_bmm/cute_top.xst" -ofn "/home/du/work/wr/wr-cores/syn/cute_wr/wr_core_demo_bmm/cute_top.syr"
ngdbuild -intstyle ise -bm cute.bmm -dd _ngo -nt timestamp -uc /home/du/work/wr/wr-cores/top/cute_wr/wr_core_demo/cute_top.ucf -p xc6slx45t-fgg484-3 cute_top.ngc cute_top.ngd
map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off -o cute_top_map.ncd cute_top.ngd cute_top.pcf
par -w -intstyle ise -ol high -mt off cute_top_map.ncd cute_top.ncd cute_top.pcf
#trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml cute_top.twx cute_top.ncd -o cute_top.twr cute_top.pcf
bitgen -intstyle ise -f cute_top.ut cute_top.ncd
data2mem -bm cute_bd.bmm -bd wrc.elf -bt cute_top.bit -o b cute_top_wrc.bit
top/cute_wr/wr_core_demo/cute.bmm 0 → 100644
View file @ 065cc1de
/* FILE : fpga.bmm
* Define a BRAM map for the LM32 memory "xwb_dpram".
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 46 ramloops and each RAMB16
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 45 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory "xwb_dpram"
* g_dpram_size = 94208/4
* 46 stacks of size 2048 bytes is 94208 bytes
*
****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory RAMB16 [0x00000000:0x00016FFF]
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram1 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram2 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram3 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram4 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram5 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram6 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram7 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram8 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram9 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram10 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram11 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram12 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram13 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram14 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram15 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram16 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram17 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram18 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram19 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram20 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram21 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram22 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram23 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram24 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram25 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram26 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram27 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram28 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram29 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram30 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram31 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram32 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram33 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram34 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram35 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram36 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram37 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram38 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram39 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram40 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram41 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram42 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram43 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram44 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram45 [31:0];
END_BUS_BLOCK;
BUS_BLOCK
U_WR_CORE/WRPC/DPRAM/U_DPRAM/gen_single_clk.U_RAM_SC/Mram_ram46 [31:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
top/cute_wr/wr_core_demo/cute_top.vhd
View file @ 065cc1de
......@@ -36,8 +36,8 @@ entity cute_top is
-- Font panel LEDs
LED_RED : out std_logic;
LED_GREEN : out std_logic;
LED_TEST : out std_logic;
LED_TEST : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
dac_clr_n_o : out std_logic;
......@@ -78,7 +78,7 @@ entity cute_top is
----------------------------------------
-- PPS
---------------------------------------
pps_o : out std_logic
pps_o : out std_logic
);
end cute_top;
......@@ -359,7 +359,7 @@ begin
led_divider <= led_divider + 1;
end if;
end process;
LED_TEST <= led_divider(23);
fpga_scl_b <= '0' when wrc_scl_o = '0' else 'Z';
......@@ -383,8 +383,8 @@ begin
g_with_external_clock_input => true,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "wrc.ram",
g_dpram_size => 94208/4, --23552,
g_dpram_initf => "",
g_dpram_size => 94208/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
......@@ -416,7 +416,7 @@ begin
led_act_o => LED_RED,
led_link_o => LED_GREEN,
scl_o => wrc_scl_o,
scl_i => wrc_scl_i,
sda_o => wrc_sda_o,
......@@ -437,7 +437,7 @@ begin
slave_i => wrc_slave_i,
slave_o => wrc_slave_o,
aux_master_o => etherbone_cfg_in,
aux_master_i => etherbone_cfg_out,
......
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