platform/altera: update Arria5 PHY with newer version, add default WR PLLs and introduce Altera WR platform wrapper

- Use the built-in 8b10b encoding/decoding provided by the Altera arria5_phy megafunction. This removes the need for
  the custom encoders/decoders, most of the processes at the end of the top-level vhd file, as well as the need for
  the tx_clk_i port and the two generics.

- Repurpose drop_link_i to reset the two megafunctions (arria5_phy_reconf and arria5_phy).

- Removed the Altera clock controllers. The system works fine without them and they only add skew to the clocks.

- Add tx_clk_o port so that we can pass the tx clock to the phy_ref_clk_i of WR PTP core.

- Introduce 8- and 16-bit PCS variants

- Introduce default PLLs for WR:
  * 1x DMTD PLL:  20MHz clock input, 62.5MHz clock output
  * 1x SYS  PLL: 125MHz clock input, 125MHz, 62.5MHz clock outputs
  * 1x EXT  PLL:  10MHz clock input, 125MHz clock output

- Reset all blocks properly and make sure that phy_ready is syncrhonised to phy_rx_clk