The problems with white rabbit reliability on arria5 were due to
two problems, both due to the WR reference fPLL.

Problem #1:

The fPLLs do not lock properly at power-on. They often ended up with
outputs that are aligned to the VCO but not the input clock. This
caused problems because it destroys the ref-tx phase relationship.

This is solved by including a core to reset the PLLs.

Problem #2:

Both the fPLL and transceiver introduce delay relative to the WR input
clock. Unfortunately, timequest does NOT analysis this phase relationship.
In order to ensure a safe transfer between the domains, we must:
a) logic lock the clk_tx and clk_ref registers beside each other
b) find the right fPLL offset to feed the clk_tx

I tried every nanosecond phase offset and recorded the results of WR below:
   0 xoxoooooxxxxxx
1000 ................
2000 ................
3000 ...............
4000 ............
5000 .x.xx.xx.x..xxx
6000 xxxxxxxxxxxxxxx
7000 xxxxxxxxxxxxxx

. = successful track
x = sync phase hangs at -4000ps
o = track phase that goes crazy