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WR Streamers provide the user with a FIFO-like interface over Ethernet
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(See figure below). WR Streamers comprises VHDL modules to ensure data
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communication as well statistics on transceiver performance.
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communication as well statistics on transceiver performance.
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Wr Streamers come included as of [Release 4 of the
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WRPC](/Current-release), instantiated inside the xwrc\_board\_common.vhd
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module. They can be enabled by setting the @ g\_fabric\_iface@ generic
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to
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WRPC](/wrpc-release-v40), instantiated inside the
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xwrc\_board\_common.vhd module. They can be enabled by setting the @
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g\_fabric\_iface@ generic to
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`STREAMERS`.
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![](/uploads/21b064f7c8ddaba77f1b49ed4a952f30/streamers-overview-small.jpg)
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-----
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## Streamers principles of data transfer
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- **Tx Streamer** transfers **data words** that are of width (n \* 16)
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bits. The width is defined by generic `data_width` (in
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`g_tx_streamer_params` and `g_rx_streamer_params`) that must be
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identical for the Tx and Rx Streamer.
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- **Data words** can be grouped in **blocks** of any size with upper
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limit defined by `max_words_per_frame` (in `g_tx_streamer_params`) ,
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each **block** has independent sequence number and CRC.
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- A stream of **data words** arranged in one or more **blocks** is
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encapsulated into an Ethernet Frame. At transmission, the frame is
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timestamped and the timestamp included in the frame.
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- Ethernet Frame is sent when one of the following is true:
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- A complete **block** was written to the buffer of the Tx
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Streamer, and the number of **data words** waiting for
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transmission exceeds the number defined by generic
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`g_tx_threshold` (in `g_tx_streamer_params`),
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- There are **data words** in the buffer of the Tx Streamer, and
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the time elapsed from the latest write to Tx Streamer exceeded
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timeout defined by generic `timeout` (in
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`g_tx_streamer_params`),
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- The user asserts `tx_flush_i` to explicitly request transmission
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of the data that has been written to the buffer of the Tx
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Streamer.
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A [simulation](/WR-Streamers-Simulation) of the Tx and Rx streamer can
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be run in order to understand how some of these features work in
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practice.
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-----
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## Encapsulation of **data words** and **blocks** into Ethernet Frame
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## Detailed information about WR Streamers
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The number of **data words** grouped into **blocks** is specified by the
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user who indicates the last **data word**. Inside the frame, each
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*block** ends with a CRC and an *escape code* (`0xCAFE`).
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The Streamer Frame consists of a transmission timestamp and a collection
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of **blocks**, it is sent in the payload of an Ethernet Frame, as
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depicted in the figure below.
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Each **block** starts with an ID number
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- the ID number of the **block** that immediately follows the Ethernet
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Header, is the sequence number of the frame
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- the ID number of the subsequent **blocks**, is the inter-frame
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sequence number of the
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*block**
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![](/uploads/e9f6b568d102f612b4e1e034378629bb/Streamer-frame.v2.jpg)
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- [Principle of Operation](/wr-streamers-principle-of-operation)
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- [Top-level module](/wr-streamers-module) (includes: [TX and RX
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streamer](/txrx-streamers) and
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[statistics](/wr-streamer-statistics))
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- [Testbenches and simulations](/wr-streamers-simulation)
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- [WR PTP Core project that includes WR Streamers as an
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option](/Wrpc-core)
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-----
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## WR streamers module
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The `xwr_streamers.vhd` module (located in modules/wr\_streamers folder
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of [wr-cores](https://www.ohwr.org/project/wr-cores/tree/master))
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provides a [WR PTP Core](/Wrpc-core) -compatible communication. It is
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meant to be a used as a building block in WR-based nodes.
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Additionally to transmission and reception of data, it provides advanced
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diagnostics and debugging capabilities that can be accessed via SNMP and
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WB registers (via PCI or VME).
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- It includes the following sub-modules:
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- \*[TX streamer](/TxRx-Streamers)* (`xtx_streamer.vhd`) - Takes a
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series of data words and encapsulates them into Ethernet Frames
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to be transmitted over the WR fabric interface.
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- \*[RX streamer](/TxRx-Streamers)* (`xrx_streamer.vhd`) -
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Receives Ethernet frames via the WR fabric interface and decodes
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them into a series of data words .
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- [Statistics](/WR) Streamer statistics
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(`xrtx_streamers_stats.vhd`)
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- WB config and status register
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(`wr_streamers_wb.vhd`)
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![](/uploads/998ae788493b5ba43685d5611bd7ee37/xwr_streamers_small.png)
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### **Interface of the `xwr_streamers.vhd` module**
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- **Configuration**
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* `g_streamers_op_mode` - Indicates whether this module instantiates
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both TX and RX streamers (set to `TX_AND_RX`) or only one
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of them. An application that only receives or only transmits might want
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to use `RX_ONLY` or `TX_ONLY` mode in order to save resources.
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* `g_tx_streamer_params` - Tx streamer generics stored in one record:
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data\_width, buffer\_size, threshold, max\_words\_per\_frame, timeout,
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escape\_code\_disable - they map into Transmit Streamer module generics
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described in detail in [Transceiver
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|
configuration](TxRx-Streamers#transceiver-configuration).
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* `g_rx_streamer_params` - Rx streamer generics stored in one record:
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data\_width, buffer\_size, escape\_code\_disable,
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expected\_words\_number - they map into Receive Streamer module generics
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|
described in detail in [Transceiver
|
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|
configuration](TxRx-Streamers#transceiver-configuration) for details.
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* `g_stats_cnt_width` - Width of statistics counters: frame
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rx/tx/lost, block lost, counter of accumuted latency (minimum 15 bits,
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max 64).
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* `g_stats_acc_width` - Width of latency accumulator (max value 64)
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.
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* `g_slave_mode` - Specifies wishbone interface mode.
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* `g_slave_granularity` - Set wishbone address granularity.
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- **WR timing input** - described in details here
|
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|
[here](TxRx-Streamers#wr-timing-input)
|
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|
- clk\_ref\_i
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- tm\_time\_valid\_i
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- tm\_tai\_i
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- tm\_cycles\_i
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- link\_ok\_i
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|
<!-- end list -->
|
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|
|
- **FIFO-like data interface** - described in details
|
|
|
[here](TxRx-Streamers#fifo-like-interface-\(tx-and-rx-streamer)).
|
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|
|
|
* **Input to Tx**
|
|
|
*\* tx\_dreq\_o
|
|
|
*\* tx\_data\_i
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|
|
*\* tx\_valid\_i
|
|
|
*\* tx\_last\_p1\_i
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|
|
*\* tx\_flush\_p1\_i
|
|
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|
|
|
* **Output from Rx**
|
|
|
*\* rx\_dreq\_i
|
|
|
*\* rx\_data\_o
|
|
|
*\* rx\_valid\_o
|
|
|
*\* rx\_first\_p1\_o
|
|
|
*\* rx\_last\_p1\_o
|
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|
|
|
|
- **Interface for configuration and diagnostics**
|
|
|
|
|
|
* **Direct network configuration** using input signals organized in
|
|
|
records (see details
|
|
|
[here](TxRx-Streamers#networking-configuration-tx-and-rx-streamer)):
|
|
|
*\* tx\_streamer\_cfg\_i
|
|
|
*\* rx\_streamer\_cfg\_i
|
|
|
|
|
|
* **Wishbone-based access** that can be used to overrite the *Direct
|
|
|
network configuration* (i.e. tx\_streamer\_cfg\_i and
|
|
|
rx\_streamer\_cfg\_i) and to read streamers statistics for diagnostics,
|
|
|
it is located in the address-space of WR PTP Core (offset 0x20700), the
|
|
|
[WB memory
|
|
|
map](https://www.ohwr.org/project/wr-cores/uploads/123c8f37ddad8747f18e780978d7bc03/wr_streamers_wb.pdf).
|
|
|
*\* wb\_slave\_i
|
|
|
*\* wb\_slave\_o
|
|
|
|
|
|
* **32-bit array** that is used by the WR PTP Core to read streamers
|
|
|
statistics for diagnostics, WR PTP Core exposes these data via SNMP and
|
|
|
shell interface (command diag)
|
|
|
*\* snmp\_array\_i
|
|
|
*\*
|
|
|
snmp\_array\_o
|
|
|
|
|
|
### Projects that use WR Streamers
|
|
|
|
|
|
- [BTrain-over-WhiteRabbit](https://gitlab.cern.ch/BTrain-TEAM/Btrain-over-WhiteRabbit/wikis/home)
|
|
|
|
|
|
-----
|
|
|
|
|
|
## Project Status
|
|
|
### Project Status
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
... | ... | |