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# Interface of Transmit and Receive Streamer modules
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The Transmit and Receive Streamers are xtx\_streamer.vhd and
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xrx\_streamer.vhd located in modules/wr\_streamers folder of
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The Transmit and Receive Streamers are `xtx_streamer.vhd` and
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`xrx_streamer.vhd` located in modules/wr\_streamers folder of
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[wr-cores](https://www.ohwr.org/project/wr-cores/tree/master) .
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### **Transceiver configuration:**
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of Tx/Rx buffer, in data words. In the case of the Tx streamer,
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it is recommended that this value exceeds 2\*g\_tx\_threshold
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(Description to follow).
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<!-- end list -->
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- `g_use_ref_clk_for_data` - when non-zero, the datapath (tx_/rx_ ports) are in the clk_ref_i
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clock domain instead of clk_sys_i. This is a must for fixed latency mode if
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clk_sys_i is asynchronous (i.e. not locked) to the WR timing.
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- `g_simulation` - when set to 1, some processes run faster (startaup-timer for tx, TAI second for RX
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- **Tx specific**
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- `g_tx_threshold` - Generic defines minimum number of data words
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- `g_simulation` and `g_sim_startup_cnt` - **Simulation specific**
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generics. Used in order to avoid long simulation delays due to
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external module startup.
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<!-- end list -->
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- `g_clk_ref_rate` - rate of the White Rabbit reference clock.
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By default, this clock is 125MHz for WR Nodes. There are some WR Nodes that work with 62.5MHz.
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- `g_sim_startup_cnt` - startup counter, used only in simulatin mode (value in 16ns cycles)
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- **Rx specific**
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- `g_expected_words_number` - generic defines the number of words
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that is expected by the receiver. This is a legacy feature, when
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a non-zero value, and combined with setting the
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`g_escape_code_disable` generic in both tx and rx to `TRUE`,
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this feature can be enabled (Though **not recommended**).
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- `g_sim_cycle_counter_range` - shorten the duration of second to see TAI seconds for simulation only (i.e. only if g_simulation = 1)
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### **Networking configuration (Tx and Rx Streamer):**
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... | ... | |