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White Rabbit core collection
Wiki
Development instructions
Development instructions
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13 years ago
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Tomasz Wlostowski
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# Development
*Coding conventions:*
*
In general, the OHR VHDL coding guidelines should be followed. However,
due to large complexity of some of the modules, there are some
exceptions:
-
you must not prefix signals with
`s_`
.
-
if the module inteface comprises multiple repetitive signals, use
structures instead of flattened
`std_logic`
ports. This makes the
interconnections between the modules much easier to understand and
less error prone. For compatibility with Verilog and gate-level
simulations, you should provide a module with flattened ports. Names
of modules with structs in ports are prefixed with
`x`
, for
example:
\-
- version with structs
entity xwr
\_
module is
port (
wb
\_
i : t
\_
wishbone
\_
slave
\_
in;
wb
\_
o : t
\_
wishbone
\_
slave
\_
out
);
end xwr
\_
module;
\-
- version without structs
entity wr
\_
module is
port (
wb
\_
adr
\_
i : in std
\_
logic
\_
vector;
wb
\_
dat
\_
i : in std
\_
logic
\_
vector;
wb
\_
ack
\_
o : out std
\_
logic;
);
end wr
\_
module;
-
do not type in UPPERCASE.
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