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Development-instructions.md

+# Development
+
+*Coding conventions:**  
+In general, the OHR VHDL coding guidelines should be followed. However,
+due to large complexity of some of the modules, there are some
+exceptions:
+
+  - you must not prefix signals with `s_`. 
+  - if the module inteface comprises multiple repetitive signals, use
+    structures instead of flattened `std_logic` ports. This makes the
+    interconnections between the modules much easier to understand and
+    less error prone. For compatibility with Verilog and gate-level
+    simulations, you should provide a module with flattened ports. Names
+    of modules with structs in ports are prefixed with `x`, for
+    example:  
+    \-- version with structs  
+    entity xwr\_module is  
+    port (  
+    wb\_i : t\_wishbone\_slave\_in;  
+    wb\_o : t\_wishbone\_slave\_out  
+    );  
+    end xwr\_module;
+
+\-- version without structs  
+entity wr\_module is  
+port (  
+wb\_adr\_i : in std\_logic\_vector;  
+wb\_dat\_i : in std\_logic\_vector;  
+wb\_ack\_o : out std\_logic;  
+);  
+end wr\_module;
+
+  - do not type in UPPERCASE. 
+